drm/gma500: Code cleanup - inline documentation
Improve readability by adding/changing inline documentation Signed-off-by: Arthur Borsboom <arthurborsboom@gmail.com> Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>hifive-unleashed-5.1
Arthur Borsboom
Patrik Jakobsson
parent
f90cd811ae
commit
9083eb381c
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@ -39,11 +39,25 @@
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static struct drm_driver driver;
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static int psb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
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/*
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* The table below contains a mapping of the PCI vendor ID and the PCI Device ID
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* to the different groups of PowerVR 5-series chip designs
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*
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* 0x8086 = Intel Corporation
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*
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* PowerVR SGX535 - Poulsbo - Intel GMA 500, Intel Atom Z5xx
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* PowerVR SGX535 - Moorestown - Intel GMA 600
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* PowerVR SGX535 - Oaktrail - Intel GMA 600, Intel Atom Z6xx, E6xx
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* PowerVR SGX540 - Medfield - Intel Atom Z2460
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* PowerVR SGX544MP2 - Medfield -
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* PowerVR SGX545 - Cedartrail - Intel GMA 3600, Intel Atom D2500, N2600
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* PowerVR SGX545 - Cedartrail - Intel GMA 3650, Intel Atom D2550, D2700,
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* N2800
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*/
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static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
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{ 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
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{ 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
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#if defined(CONFIG_DRM_GMA600)
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/* Atom E620 */
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{ 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
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{ 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
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{ 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
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@ -151,8 +165,7 @@ static int psb_driver_unload(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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/* Kill vblank etc here */
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/* TODO: Kill vblank etc here */
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if (dev_priv) {
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if (dev_priv->backlight_device)
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@ -222,6 +235,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags)
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struct gma_encoder *gma_encoder;
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struct psb_gtt *pg;
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/* allocating and initializing driver private data */
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dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
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if (dev_priv == NULL)
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return -ENOMEM;
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@ -321,6 +335,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags)
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acpi_video_register();
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/* Setup vertical blanking handling */
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ret = drm_vblank_init(dev, dev_priv->num_pipe);
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if (ret)
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goto out_err;
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@ -366,11 +381,11 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags)
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return ret;
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psb_intel_opregion_enable_asle(dev);
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#if 0
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/*enable runtime pm at last*/
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/* Enable runtime pm at last */
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pm_runtime_enable(&dev->pdev->dev);
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pm_runtime_set_active(&dev->pdev->dev);
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#endif
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/*Intel drm driver load is done, continue doing pvr load*/
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/* Intel drm driver load is done, continue doing pvr load */
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return 0;
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out_err:
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psb_driver_unload(dev);
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@ -61,10 +61,7 @@ enum {
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#define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130)
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#define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0)
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/*
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* Hardware offsets
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*/
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/* Hardware offsets */
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#define PSB_VDC_OFFSET 0x00000000
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#define PSB_VDC_SIZE 0x000080000
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#define MRST_MMIO_SIZE 0x0000C0000
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@ -72,16 +69,14 @@ enum {
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#define PSB_SGX_SIZE 0x8000
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#define PSB_SGX_OFFSET 0x00040000
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#define MRST_SGX_OFFSET 0x00080000
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/*
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* PCI resource identifiers
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*/
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/* PCI resource identifiers */
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#define PSB_MMIO_RESOURCE 0
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#define PSB_AUX_RESOURCE 0
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#define PSB_GATT_RESOURCE 2
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#define PSB_GTT_RESOURCE 3
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/*
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* PCI configuration
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*/
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/* PCI configuration */
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#define PSB_GMCH_CTRL 0x52
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#define PSB_BSM 0x5C
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#define _PSB_GMCH_ENABLED 0x4
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@ -89,37 +84,29 @@ enum {
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#define _PSB_PGETBL_ENABLED 0x00000001
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#define PSB_SGX_2D_SLAVE_PORT 0x4000
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/* To get rid of */
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/* TODO: To get rid of */
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#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
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#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
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/*
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* SGX side MMU definitions (these can probably go)
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*/
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/* SGX side MMU definitions (these can probably go) */
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/*
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* Flags for external memory type field.
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*/
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/* Flags for external memory type field */
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#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
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#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
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#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
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/*
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* PTE's and PDE's
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*/
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/* PTE's and PDE's */
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#define PSB_PDE_MASK 0x003FFFFF
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#define PSB_PDE_SHIFT 22
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#define PSB_PTE_SHIFT 12
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/*
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* Cache control
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*/
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/* Cache control */
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#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
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#define PSB_PTE_WO 0x0002 /* Write only */
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#define PSB_PTE_RO 0x0004 /* Read only */
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#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
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/*
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* VDC registers and bits
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*/
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/* VDC registers and bits */
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#define PSB_MSVDX_CLOCKGATING 0x2064
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#define PSB_TOPAZ_CLOCKGATING 0x2068
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#define PSB_HWSTAM 0x2098
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@ -285,10 +272,7 @@ struct intel_gmbus {
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u32 reg0;
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};
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/*
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* Register offset maps
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*/
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/* Register offset maps */
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struct psb_offset {
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u32 fp0;
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u32 fp1;
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@ -322,9 +306,7 @@ struct psb_offset {
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* update the register cache instead.
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*/
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/*
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* Common status for pipes.
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*/
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/* Common status for pipes */
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struct psb_pipe {
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u32 fp0;
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u32 fp1;
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@ -484,35 +466,24 @@ struct drm_psb_private {
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struct psb_mmu_driver *mmu;
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struct psb_mmu_pd *pf_pd;
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/*
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* Register base
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*/
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/* Register base */
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uint8_t __iomem *sgx_reg;
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uint8_t __iomem *vdc_reg;
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uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
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uint32_t gatt_free_offset;
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/*
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* Fencing / irq.
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*/
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/* Fencing / irq */
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uint32_t vdc_irq_mask;
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uint32_t pipestat[PSB_NUM_PIPE];
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spinlock_t irqmask_lock;
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/*
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* Power
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*/
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/* Power */
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bool suspended;
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bool display_power;
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int display_count;
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/*
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* Modesetting
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*/
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/* Modesetting */
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struct psb_intel_mode_device mode_dev;
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bool modeset; /* true if we have done the mode_device setup */
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@ -520,15 +491,10 @@ struct drm_psb_private {
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struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
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uint32_t num_pipe;
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/*
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* OSPM info (Power management base) (can go ?)
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*/
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/* OSPM info (Power management base) (TODO: can go ?) */
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uint32_t ospm_base;
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/*
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* Sizes info
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*/
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/* Sizes info */
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u32 fuse_reg_value;
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u32 video_device_fuse;
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@ -548,9 +514,7 @@ struct drm_psb_private {
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struct drm_property *broadcast_rgb_property;
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struct drm_property *force_audio_property;
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/*
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* LVDS info
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*/
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/* LVDS info */
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int backlight_duty_cycle; /* restore backlight to this value */
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bool panel_wants_dither;
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struct drm_display_mode *panel_fixed_mode;
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@ -584,34 +548,23 @@ struct drm_psb_private {
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/* Oaktrail HDMI state */
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struct oaktrail_hdmi_dev *hdmi_priv;
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/*
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* Register state
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*/
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/* Register state */
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struct psb_save_area regs;
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/* MSI reg save */
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uint32_t msi_addr;
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uint32_t msi_data;
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/*
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* Hotplug handling
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*/
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/* Hotplug handling */
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struct work_struct hotplug_work;
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/*
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* LID-Switch
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*/
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/* LID-Switch */
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spinlock_t lid_lock;
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struct timer_list lid_timer;
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struct psb_intel_opregion opregion;
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u32 lid_last_state;
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/*
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* Watchdog
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*/
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/* Watchdog */
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uint32_t apm_reg;
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uint16_t apm_base;
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@ -631,9 +584,7 @@ struct drm_psb_private {
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/* 2D acceleration */
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spinlock_t lock_2d;
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/*
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* Panel brightness
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*/
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/* Panel brightness */
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int brightness;
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int brightness_adjusted;
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@ -666,10 +617,7 @@ struct drm_psb_private {
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};
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/*
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* Operations for each board type
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*/
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/* Operations for each board type */
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struct psb_ops {
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const char *name;
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unsigned int accel_2d:1;
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@ -723,10 +671,7 @@ static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
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return (struct drm_psb_private *) dev->dev_private;
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}
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/*
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*psb_irq.c
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*/
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/* psb_irq.c */
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extern irqreturn_t psb_irq_handler(int irq, void *arg);
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extern int psb_irq_enable_dpst(struct drm_device *dev);
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extern int psb_irq_disable_dpst(struct drm_device *dev);
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@ -749,24 +694,17 @@ psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
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extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
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/*
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* framebuffer.c
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*/
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/* framebuffer.c */
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extern int psbfb_probed(struct drm_device *dev);
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extern int psbfb_remove(struct drm_device *dev,
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struct drm_framebuffer *fb);
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/*
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* accel_2d.c
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*/
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/* accel_2d.c */
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extern void psbfb_copyarea(struct fb_info *info,
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const struct fb_copyarea *region);
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extern int psbfb_sync(struct fb_info *info);
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extern void psb_spank(struct drm_psb_private *dev_priv);
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/*
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* psb_reset.c
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*/
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/* psb_reset.c */
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extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
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extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
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extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
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@ -825,9 +763,7 @@ extern const struct psb_ops mdfld_chip_ops;
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/* cdv_device.c */
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extern const struct psb_ops cdv_chip_ops;
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/*
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* Debug print bits setting
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*/
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/* Debug print bits setting */
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#define PSB_D_GENERAL (1 << 0)
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#define PSB_D_INIT (1 << 1)
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#define PSB_D_IRQ (1 << 2)
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@ -843,10 +779,7 @@ extern const struct psb_ops cdv_chip_ops;
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extern int drm_idle_check_interval;
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/*
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* Utilities
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*/
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/* Utilities */
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static inline u32 MRST_MSG_READ32(uint port, uint offset)
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{
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int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
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