x86: Remove the calgary IOMMU driver
The calgary IOMMU was only used on high-end IBM systems in the early x86_64 age and has no known users left. Remove it to avoid having to touch it for pending changes to the DMA API. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20191113071836.21041-2-hch@lst.dealistair/sunxi64-5.5-dsi
Christoph Hellwig
Thomas Gleixner
parent
44eb5a7e5d
commit
90dc392fc4
10
MAINTAINERS
10
MAINTAINERS
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@ -3629,16 +3629,6 @@ L: cake@lists.bufferbloat.net (moderated for non-subscribers)
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S: Maintained
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F: net/sched/sch_cake.c
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CALGARY x86-64 IOMMU
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M: Muli Ben-Yehuda <mulix@mulix.org>
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M: Jon Mason <jdmason@kudzu.us>
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L: iommu@lists.linux-foundation.org
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S: Maintained
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F: arch/x86/kernel/pci-calgary_64.c
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F: arch/x86/kernel/tce_64.c
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F: arch/x86/include/asm/calgary.h
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F: arch/x86/include/asm/tce.h
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CAN NETWORK DRIVERS
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M: Wolfgang Grandegger <wg@grandegger.com>
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M: Marc Kleine-Budde <mkl@pengutronix.de>
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@ -932,36 +932,6 @@ config GART_IOMMU
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If unsure, say Y.
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config CALGARY_IOMMU
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bool "IBM Calgary IOMMU support"
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select IOMMU_HELPER
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select SWIOTLB
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depends on X86_64 && PCI
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---help---
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Support for hardware IOMMUs in IBM's xSeries x366 and x460
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systems. Needed to run systems with more than 3GB of memory
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properly with 32-bit PCI devices that do not support DAC
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(Double Address Cycle). Calgary also supports bus level
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isolation, where all DMAs pass through the IOMMU. This
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prevents them from going anywhere except their intended
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destination. This catches hard-to-find kernel bugs and
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mis-behaving drivers and devices that do not use the DMA-API
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properly to set up their DMA buffers. The IOMMU can be
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turned off at boot time with the iommu=off parameter.
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Normally the kernel will make the right choice by itself.
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If unsure, say Y.
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config CALGARY_IOMMU_ENABLED_BY_DEFAULT
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def_bool y
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prompt "Should Calgary be enabled by default?"
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depends on CALGARY_IOMMU
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---help---
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Should Calgary be enabled by default? if you choose 'y', Calgary
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will be used (if it exists). If you choose 'n', Calgary will not be
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used even if it exists. If you choose 'n' and would like to use
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Calgary anyway, pass 'iommu=calgary' on the kernel command line.
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If unsure, say Y.
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config MAXSMP
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bool "Enable Maximum number of SMP Processors and NUMA Nodes"
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depends on X86_64 && SMP && DEBUG_KERNEL
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@ -25,7 +25,6 @@ CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_MODULE_FORCE_UNLOAD=y
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CONFIG_SMP=y
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CONFIG_CALGARY_IOMMU=y
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CONFIG_NR_CPUS=64
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CONFIG_SCHED_SMT=y
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CONFIG_PREEMPT_VOLUNTARY=y
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@ -1,57 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Derived from include/asm-powerpc/iommu.h
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*
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* Copyright IBM Corporation, 2006-2007
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*
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* Author: Jon Mason <jdmason@us.ibm.com>
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* Author: Muli Ben-Yehuda <muli@il.ibm.com>
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*/
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#ifndef _ASM_X86_CALGARY_H
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#define _ASM_X86_CALGARY_H
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#include <linux/spinlock.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/timer.h>
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#include <asm/types.h>
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struct iommu_table {
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const struct cal_chipset_ops *chip_ops; /* chipset specific funcs */
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unsigned long it_base; /* mapped address of tce table */
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unsigned long it_hint; /* Hint for next alloc */
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unsigned long *it_map; /* A simple allocation bitmap for now */
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void __iomem *bbar; /* Bridge BAR */
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u64 tar_val; /* Table Address Register */
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struct timer_list watchdog_timer;
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spinlock_t it_lock; /* Protects it_map */
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unsigned int it_size; /* Size of iommu table in entries */
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unsigned char it_busno; /* Bus number this table belongs to */
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};
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struct cal_chipset_ops {
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void (*handle_quirks)(struct iommu_table *tbl, struct pci_dev *dev);
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void (*tce_cache_blast)(struct iommu_table *tbl);
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void (*dump_error_regs)(struct iommu_table *tbl);
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};
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#define TCE_TABLE_SIZE_UNSPECIFIED ~0
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#define TCE_TABLE_SIZE_64K 0
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#define TCE_TABLE_SIZE_128K 1
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#define TCE_TABLE_SIZE_256K 2
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#define TCE_TABLE_SIZE_512K 3
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#define TCE_TABLE_SIZE_1M 4
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#define TCE_TABLE_SIZE_2M 5
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#define TCE_TABLE_SIZE_4M 6
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#define TCE_TABLE_SIZE_8M 7
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extern int use_calgary;
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#ifdef CONFIG_CALGARY_IOMMU
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extern int detect_calgary(void);
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#else
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static inline int detect_calgary(void) { return -ENODEV; }
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#endif
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#endif /* _ASM_X86_CALGARY_H */
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@ -4,20 +4,6 @@
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#ifdef __KERNEL__
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#ifdef CONFIG_CALGARY_IOMMU
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static inline void *pci_iommu(struct pci_bus *bus)
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{
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struct pci_sysdata *sd = bus->sysdata;
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return sd->iommu;
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}
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static inline void set_pci_iommu(struct pci_bus *bus, void *val)
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{
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struct pci_sysdata *sd = bus->sysdata;
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sd->iommu = val;
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}
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#endif /* CONFIG_CALGARY_IOMMU */
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extern int (*pci_config_read)(int seg, int bus, int dev, int fn,
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int reg, int len, u32 *value);
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extern int (*pci_config_write)(int seg, int bus, int dev, int fn,
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@ -1,35 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This file is derived from asm-powerpc/tce.h.
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*
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* Copyright (C) IBM Corporation, 2006
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*
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* Author: Muli Ben-Yehuda <muli@il.ibm.com>
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* Author: Jon Mason <jdmason@us.ibm.com>
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*/
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#ifndef _ASM_X86_TCE_H
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#define _ASM_X86_TCE_H
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extern unsigned int specified_table_size;
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struct iommu_table;
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#define TCE_ENTRY_SIZE 8 /* in bytes */
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#define TCE_READ_SHIFT 0
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#define TCE_WRITE_SHIFT 1
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#define TCE_HUBID_SHIFT 2 /* unused */
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#define TCE_RSVD_SHIFT 8 /* unused */
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#define TCE_RPN_SHIFT 12
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#define TCE_UNUSED_SHIFT 48 /* unused */
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#define TCE_RPN_MASK 0x0000fffffffff000ULL
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extern void tce_build(struct iommu_table *tbl, unsigned long index,
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unsigned int npages, unsigned long uaddr, int direction);
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extern void tce_free(struct iommu_table *tbl, long index, unsigned int npages);
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extern void * __init alloc_tce_table(void);
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extern void __init free_tce_table(void *tbl);
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extern int __init build_tce_table(struct pci_dev *dev, void __iomem *bbar);
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#endif /* _ASM_X86_TCE_H */
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@ -146,7 +146,6 @@ ifeq ($(CONFIG_X86_64),y)
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obj-$(CONFIG_AUDIT) += audit_64.o
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obj-$(CONFIG_GART_IOMMU) += amd_gart_64.o aperture_64.o
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obj-$(CONFIG_CALGARY_IOMMU) += pci-calgary_64.o tce_64.o
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obj-$(CONFIG_MMCONF_FAM10H) += mmconf-fam10h_64.o
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obj-y += vsmp_64.o
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File diff suppressed because it is too large
Load Diff
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@ -12,7 +12,6 @@
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#include <asm/dma.h>
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#include <asm/iommu.h>
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#include <asm/gart.h>
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#include <asm/calgary.h>
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#include <asm/x86_init.h>
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#include <asm/iommu_table.h>
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@ -112,11 +111,6 @@ static __init int iommu_setup(char *p)
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gart_parse_options(p);
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#ifdef CONFIG_CALGARY_IOMMU
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if (!strncmp(p, "calgary", 7))
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use_calgary = 1;
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#endif /* CONFIG_CALGARY_IOMMU */
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p += strcspn(p, ",");
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if (*p == ',')
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++p;
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@ -1,177 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* This file manages the translation entries for the IBM Calgary IOMMU.
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*
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* Derived from arch/powerpc/platforms/pseries/iommu.c
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*
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* Copyright (C) IBM Corporation, 2006
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*
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* Author: Jon Mason <jdmason@us.ibm.com>
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* Author: Muli Ben-Yehuda <muli@il.ibm.com>
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*/
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/memblock.h>
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#include <asm/tce.h>
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#include <asm/calgary.h>
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#include <asm/proto.h>
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#include <asm/cacheflush.h>
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/* flush a tce at 'tceaddr' to main memory */
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static inline void flush_tce(void* tceaddr)
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{
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/* a single tce can't cross a cache line */
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if (boot_cpu_has(X86_FEATURE_CLFLUSH))
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clflush(tceaddr);
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else
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wbinvd();
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}
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void tce_build(struct iommu_table *tbl, unsigned long index,
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unsigned int npages, unsigned long uaddr, int direction)
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{
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u64* tp;
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u64 t;
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u64 rpn;
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t = (1 << TCE_READ_SHIFT);
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if (direction != DMA_TO_DEVICE)
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t |= (1 << TCE_WRITE_SHIFT);
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tp = ((u64*)tbl->it_base) + index;
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while (npages--) {
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rpn = (virt_to_bus((void*)uaddr)) >> PAGE_SHIFT;
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t &= ~TCE_RPN_MASK;
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t |= (rpn << TCE_RPN_SHIFT);
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*tp = cpu_to_be64(t);
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flush_tce(tp);
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uaddr += PAGE_SIZE;
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tp++;
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}
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}
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void tce_free(struct iommu_table *tbl, long index, unsigned int npages)
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{
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u64* tp;
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tp = ((u64*)tbl->it_base) + index;
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while (npages--) {
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*tp = cpu_to_be64(0);
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flush_tce(tp);
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tp++;
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}
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}
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static inline unsigned int table_size_to_number_of_entries(unsigned char size)
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{
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/*
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* size is the order of the table, 0-7
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* smallest table is 8K entries, so shift result by 13 to
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* multiply by 8K
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*/
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return (1 << size) << 13;
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}
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static int tce_table_setparms(struct pci_dev *dev, struct iommu_table *tbl)
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{
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unsigned int bitmapsz;
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unsigned long bmppages;
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int ret;
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tbl->it_busno = dev->bus->number;
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/* set the tce table size - measured in entries */
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tbl->it_size = table_size_to_number_of_entries(specified_table_size);
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/*
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* number of bytes needed for the bitmap size in number of
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* entries; we need one bit per entry
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*/
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bitmapsz = tbl->it_size / BITS_PER_BYTE;
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bmppages = __get_free_pages(GFP_KERNEL, get_order(bitmapsz));
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if (!bmppages) {
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printk(KERN_ERR "Calgary: cannot allocate bitmap\n");
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ret = -ENOMEM;
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goto done;
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}
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tbl->it_map = (unsigned long*)bmppages;
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memset(tbl->it_map, 0, bitmapsz);
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tbl->it_hint = 0;
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spin_lock_init(&tbl->it_lock);
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return 0;
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done:
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return ret;
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}
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int __init build_tce_table(struct pci_dev *dev, void __iomem *bbar)
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{
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struct iommu_table *tbl;
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int ret;
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if (pci_iommu(dev->bus)) {
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printk(KERN_ERR "Calgary: dev %p has sysdata->iommu %p\n",
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dev, pci_iommu(dev->bus));
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BUG();
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}
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tbl = kzalloc(sizeof(struct iommu_table), GFP_KERNEL);
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if (!tbl) {
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printk(KERN_ERR "Calgary: error allocating iommu_table\n");
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ret = -ENOMEM;
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goto done;
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}
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ret = tce_table_setparms(dev, tbl);
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if (ret)
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goto free_tbl;
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tbl->bbar = bbar;
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set_pci_iommu(dev->bus, tbl);
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return 0;
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free_tbl:
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kfree(tbl);
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done:
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return ret;
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}
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void * __init alloc_tce_table(void)
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{
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unsigned int size;
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size = table_size_to_number_of_entries(specified_table_size);
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size *= TCE_ENTRY_SIZE;
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return memblock_alloc_low(size, size);
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}
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void __init free_tce_table(void *tbl)
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{
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unsigned int size;
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if (!tbl)
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return;
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size = table_size_to_number_of_entries(specified_table_size);
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size *= TCE_ENTRY_SIZE;
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memblock_free(__pa(tbl), size);
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}
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