IB/mlx4: Fix SL to 802.1Q priority-bits mapping for IBoE
For IBoE, SLs 0-7 are mapped to Ethernet 802.1Q user priority bits (pbits) which are part of the VLAN tag, SLs 8-15 are reserved. Under Ethernet, the ConnectX firmware treats (decode/encode) the four bit SL field in various constructs such as QPC / UD WQE / CQE as PPP0 and not as 0PPP. This correlates well to the fact that within the vlan tag the pbits are located in bits 15-13 and not 12-14. The current code wasn't consistent around that area - the encoding was correct for the IBoE QPC.path.schedule_queue field, but was wrong for IBoE CQEs and when MLX header was built. These inconsistencies resulted in wrong SL <--> wire 802.1Q pbits mapping, which is fixed by using SL <--> PPP0 all around the place. Signed-off-by: Oren Duer <oren@mellanox.co.il> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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@ -126,7 +126,7 @@ static struct ib_ah *create_iboe_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr
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ah->av.ib.dlid = cpu_to_be16(0xc000);
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memcpy(ah->av.eth.dgid, ah_attr->grh.dgid.raw, 16);
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ah->av.eth.sl_tclass_flowlabel = cpu_to_be32(ah_attr->sl << 28);
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ah->av.eth.sl_tclass_flowlabel = cpu_to_be32(ah_attr->sl << 29);
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return &ah->ibah;
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}
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@ -715,13 +715,17 @@ repoll:
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}
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wc->slid = be16_to_cpu(cqe->rlid);
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wc->sl = be16_to_cpu(cqe->sl_vid) >> 12;
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g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
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wc->src_qp = g_mlpath_rqpn & 0xffffff;
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wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
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wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
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wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
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wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->status, cqe->checksum);
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if (rdma_port_get_link_layer(wc->qp->device,
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(*cur_qp)->port) == IB_LINK_LAYER_ETHERNET)
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wc->sl = be16_to_cpu(cqe->sl_vid) >> 13;
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else
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wc->sl = be16_to_cpu(cqe->sl_vid) >> 12;
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}
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return 0;
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@ -962,7 +962,7 @@ static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
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if (is_eth) {
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path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
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((port - 1) << 6) | ((ah->sl & 7) << 3) | ((ah->sl & 8) >> 1);
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((port - 1) << 6) | ((ah->sl & 7) << 3);
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if (!(ah->ah_flags & IB_AH_GRH))
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return -1;
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@ -1437,7 +1437,7 @@ static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
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u16 pcp;
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sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
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pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 27 & 3) << 13;
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pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
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sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
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}
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} else {
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