Merge branch 'drm-fixes-4.5' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
radeon and amdgpu fixes for 4.5. Three regression fixes and some fixups for the error handling in the vblank regression fixes from earlier. * 'drm-fixes-4.5' of git://people.freedesktop.org/~agd5f/linux: Revert "drm/radeon/pm: adjust display configuration after powerstate" drm/amdgpu/dp: add back special handling for NUTMEG drm/radeon/dp: add back special handling for NUTMEG drm/radeon: Fix error handling in radeon_flip_work_func. drm/amdgpu: Fix error handling in amdgpu_flip_work_func.
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913830147a
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@ -96,7 +96,7 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
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* In practice this won't execute very often unless on very fast
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* machines because the time window for this to happen is very small.
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*/
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while (amdgpuCrtc->enabled && repcnt--) {
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while (amdgpuCrtc->enabled && --repcnt) {
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/* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
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* start in hpos, and to the "fudged earlier" vblank start in
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* vpos.
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@ -112,13 +112,13 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
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break;
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/* Sleep at least until estimated real start of hw vblank */
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5);
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if (min_udelay > vblank->framedur_ns / 2000) {
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/* Don't wait ridiculously long - something is wrong */
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repcnt = 0;
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break;
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}
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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usleep_range(min_udelay, 2 * min_udelay);
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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};
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@ -265,15 +265,27 @@ static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector
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unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
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unsigned lane_num, i, max_pix_clock;
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for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
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for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
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max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
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if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
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ENCODER_OBJECT_ID_NUTMEG) {
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for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
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max_pix_clock = (lane_num * 270000 * 8) / bpp;
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if (max_pix_clock >= pix_clock) {
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*dp_lanes = lane_num;
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*dp_rate = link_rates[i];
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*dp_rate = 270000;
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return 0;
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}
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}
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} else {
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for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
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for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
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max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
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if (max_pix_clock >= pix_clock) {
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*dp_lanes = lane_num;
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*dp_rate = link_rates[i];
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return 0;
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}
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}
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}
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}
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return -EINVAL;
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@ -315,15 +315,27 @@ int radeon_dp_get_dp_link_config(struct drm_connector *connector,
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unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
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unsigned lane_num, i, max_pix_clock;
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for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
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for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
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max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
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if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
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ENCODER_OBJECT_ID_NUTMEG) {
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for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
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max_pix_clock = (lane_num * 270000 * 8) / bpp;
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if (max_pix_clock >= pix_clock) {
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*dp_lanes = lane_num;
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*dp_rate = link_rates[i];
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*dp_rate = 270000;
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return 0;
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}
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}
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} else {
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for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
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for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
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max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
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if (max_pix_clock >= pix_clock) {
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*dp_lanes = lane_num;
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*dp_rate = link_rates[i];
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return 0;
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}
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}
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}
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}
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return -EINVAL;
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@ -455,7 +455,7 @@ static void radeon_flip_work_func(struct work_struct *__work)
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* In practice this won't execute very often unless on very fast
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* machines because the time window for this to happen is very small.
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*/
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while (radeon_crtc->enabled && repcnt--) {
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while (radeon_crtc->enabled && --repcnt) {
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/* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
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* start in hpos, and to the "fudged earlier" vblank start in
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* vpos.
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@ -471,13 +471,13 @@ static void radeon_flip_work_func(struct work_struct *__work)
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break;
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/* Sleep at least until estimated real start of hw vblank */
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5);
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if (min_udelay > vblank->framedur_ns / 2000) {
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/* Don't wait ridiculously long - something is wrong */
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repcnt = 0;
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break;
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}
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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usleep_range(min_udelay, 2 * min_udelay);
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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};
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@ -1079,6 +1079,8 @@ force:
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/* update display watermarks based on new power state */
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radeon_bandwidth_update(rdev);
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/* update displays */
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radeon_dpm_display_configuration_changed(rdev);
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/* wait for the rings to drain */
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for (i = 0; i < RADEON_NUM_RINGS; i++) {
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@ -1095,9 +1097,6 @@ force:
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radeon_dpm_post_set_power_state(rdev);
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/* update displays */
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radeon_dpm_display_configuration_changed(rdev);
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rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
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rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
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rdev->pm.dpm.single_display = single_display;
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