Merge branch 'next-s3c' of git://aeryn.fluff.org.uk/bjdooks/linux into devel
This commit is contained in:
commit
915166d96f
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@ -119,7 +119,7 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
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unsigned int shift = (off & 7) * 4;
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u32 con;
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if (off < 8 && chip->chip.ngpio >= 8)
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if (off < 8 && chip->chip.ngpio > 8)
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reg -= 4;
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if (s3c_gpio_is_cfg_special(cfg)) {
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@ -191,7 +191,7 @@ static struct clk init_clocks[] = {
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.id = -1,
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.parent = &clk_h,
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.enable = s3c64xx_hclk_ctrl,
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.ctrlbit = S3C_CLKCON_SCLK_UHOST,
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.ctrlbit = S3C_CLKCON_HCLK_UHOST,
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}, {
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.name = "hsmmc",
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.id = 0,
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@ -321,6 +321,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
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.get_pull = s3c_gpio_getpull_updown,
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};
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int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
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{
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return IRQ_EINT(0) + pin;
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}
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static struct s3c_gpio_chip gpio_2bit[] = {
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{
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.base = S3C64XX_GPF_BASE,
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@ -353,6 +358,7 @@ static struct s3c_gpio_chip gpio_2bit[] = {
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.base = S3C64XX_GPN(0),
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.ngpio = S3C64XX_GPIO_N_NR,
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.label = "GPN",
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.to_irq = s3c64xx_gpio2int_gpn,
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},
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}, {
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.base = S3C64XX_GPO_BASE,
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@ -88,11 +88,11 @@
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#define S3C6400_CLKDIV2_SPI0_SHIFT (0)
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/* HCLK GATE Registers */
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#define S3C_CLKCON_HCLK_BUS (1<<30)
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#define S3C_CLKCON_HCLK_SECUR (1<<29)
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#define S3C_CLKCON_HCLK_SDMA1 (1<<28)
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#define S3C_CLKCON_HCLK_SDMA2 (1<<27)
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#define S3C_CLKCON_HCLK_UHOST (1<<26)
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#define S3C_CLKCON_HCLK_3DSE (1<<31)
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#define S3C_CLKCON_HCLK_UHOST (1<<29)
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#define S3C_CLKCON_HCLK_SECUR (1<<28)
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#define S3C_CLKCON_HCLK_SDMA1 (1<<27)
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#define S3C_CLKCON_HCLK_SDMA0 (1<<26)
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#define S3C_CLKCON_HCLK_IROM (1<<25)
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#define S3C_CLKCON_HCLK_DDR1 (1<<24)
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#define S3C_CLKCON_HCLK_DDR0 (1<<23)
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