tools/testing/nvdimm: Emulate firmware activation commands
Augment the existing firmware update emulation to track activations and validate proper update vs activate sequencing. The DIMM firmware activate capability has a concept of a maximum amount of time platform firmware will quiesce the system relative to how many DIMMs are being activated in parallel. Simulate that DIMM activation happens serially, 1 second per-DIMM, and limit the max at 3 seconds. The nfit_test0 bus emulates 5 DIMMs so it will take 2 activations to update all DIMMs. Cc: Vishal Verma <vishal.l.verma@intel.com> Cc: Dave Jiang <dave.jiang@intel.com> Cc: Ira Weiny <ira.weiny@intel.com> Reported-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
This commit is contained in:
Dan Williams
Vishal Verma
parent
abfd4d9c82
commit
916566ae78
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@ -132,6 +132,9 @@ struct nd_intel_fw_activate_dimminfo {
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u8 reserved[7];
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} __packed;
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#define ND_INTEL_DIMM_FWA_ARM 1
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#define ND_INTEL_DIMM_FWA_DISARM 0
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struct nd_intel_fw_activate_arm {
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u8 activate_arm;
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u32 status;
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@ -160,6 +163,8 @@ struct nd_intel_bus_fw_activate_businfo {
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#define ND_INTEL_BUS_FWA_STATUS_NOIDLE (6 | 5 << 16)
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#define ND_INTEL_BUS_FWA_STATUS_ABORT (6 | 6 << 16)
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#define ND_INTEL_BUS_FWA_IODEV_FORCE_IDLE (0)
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#define ND_INTEL_BUS_FWA_IODEV_OS_IDLE (1)
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struct nd_intel_bus_fw_activate {
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u8 iodev_state;
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u32 status;
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@ -173,6 +173,9 @@ struct nfit_test_fw {
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u64 version;
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u32 size_received;
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u64 end_time;
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bool armed;
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bool missed_activate;
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unsigned long last_activate;
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};
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struct nfit_test {
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@ -345,7 +348,7 @@ static int nd_intel_test_finish_fw(struct nfit_test *t,
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__func__, t, nd_cmd, buf_len, idx);
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if (fw->state == FW_STATE_UPDATED) {
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/* update already done, need cold boot */
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/* update already done, need activation */
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nd_cmd->status = 0x20007;
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return 0;
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}
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@ -430,6 +433,7 @@ static int nd_intel_test_finish_query(struct nfit_test *t,
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}
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dev_dbg(dev, "%s: transition out verify\n", __func__);
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fw->state = FW_STATE_UPDATED;
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fw->missed_activate = false;
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/* fall through */
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case FW_STATE_UPDATED:
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nd_cmd->status = 0;
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@ -1178,6 +1182,134 @@ static int nd_intel_test_cmd_master_secure_erase(struct nfit_test *t,
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return 0;
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}
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static unsigned long last_activate;
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static int nvdimm_bus_intel_fw_activate_businfo(struct nfit_test *t,
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struct nd_intel_bus_fw_activate_businfo *nd_cmd,
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unsigned int buf_len)
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{
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int i, armed = 0;
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int state;
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u64 tmo;
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for (i = 0; i < NUM_DCR; i++) {
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struct nfit_test_fw *fw = &t->fw[i];
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if (fw->armed)
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armed++;
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}
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/*
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* Emulate 3 second activation max, and 1 second incremental
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* quiesce time per dimm requiring multiple activates to get all
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* DIMMs updated.
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*/
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if (armed)
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state = ND_INTEL_FWA_ARMED;
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else if (!last_activate || time_after(jiffies, last_activate + 3 * HZ))
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state = ND_INTEL_FWA_IDLE;
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else
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state = ND_INTEL_FWA_BUSY;
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tmo = armed * USEC_PER_SEC;
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*nd_cmd = (struct nd_intel_bus_fw_activate_businfo) {
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.capability = ND_INTEL_BUS_FWA_CAP_FWQUIESCE
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| ND_INTEL_BUS_FWA_CAP_OSQUIESCE
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| ND_INTEL_BUS_FWA_CAP_RESET,
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.state = state,
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.activate_tmo = tmo,
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.cpu_quiesce_tmo = tmo,
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.io_quiesce_tmo = tmo,
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.max_quiesce_tmo = 3 * USEC_PER_SEC,
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};
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return 0;
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}
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static int nvdimm_bus_intel_fw_activate(struct nfit_test *t,
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struct nd_intel_bus_fw_activate *nd_cmd,
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unsigned int buf_len)
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{
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struct nd_intel_bus_fw_activate_businfo info;
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u32 status = 0;
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int i;
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nvdimm_bus_intel_fw_activate_businfo(t, &info, sizeof(info));
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if (info.state == ND_INTEL_FWA_BUSY)
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status = ND_INTEL_BUS_FWA_STATUS_BUSY;
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else if (info.activate_tmo > info.max_quiesce_tmo)
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status = ND_INTEL_BUS_FWA_STATUS_TMO;
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else if (info.state == ND_INTEL_FWA_IDLE)
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status = ND_INTEL_BUS_FWA_STATUS_NOARM;
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dev_dbg(&t->pdev.dev, "status: %d\n", status);
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nd_cmd->status = status;
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if (status && status != ND_INTEL_BUS_FWA_STATUS_TMO)
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return 0;
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last_activate = jiffies;
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for (i = 0; i < NUM_DCR; i++) {
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struct nfit_test_fw *fw = &t->fw[i];
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if (!fw->armed)
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continue;
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if (fw->state != FW_STATE_UPDATED)
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fw->missed_activate = true;
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else
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fw->state = FW_STATE_NEW;
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fw->armed = false;
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fw->last_activate = last_activate;
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}
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return 0;
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}
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static int nd_intel_test_cmd_fw_activate_dimminfo(struct nfit_test *t,
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struct nd_intel_fw_activate_dimminfo *nd_cmd,
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unsigned int buf_len, int dimm)
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{
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struct nd_intel_bus_fw_activate_businfo info;
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struct nfit_test_fw *fw = &t->fw[dimm];
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u32 result, state;
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nvdimm_bus_intel_fw_activate_businfo(t, &info, sizeof(info));
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if (info.state == ND_INTEL_FWA_BUSY)
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state = ND_INTEL_FWA_BUSY;
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else if (info.state == ND_INTEL_FWA_IDLE)
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state = ND_INTEL_FWA_IDLE;
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else if (fw->armed)
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state = ND_INTEL_FWA_ARMED;
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else
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state = ND_INTEL_FWA_IDLE;
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result = ND_INTEL_DIMM_FWA_NONE;
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if (last_activate && fw->last_activate == last_activate &&
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state == ND_INTEL_FWA_IDLE) {
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if (fw->missed_activate)
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result = ND_INTEL_DIMM_FWA_NOTSTAGED;
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else
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result = ND_INTEL_DIMM_FWA_SUCCESS;
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}
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*nd_cmd = (struct nd_intel_fw_activate_dimminfo) {
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.result = result,
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.state = state,
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};
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return 0;
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}
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static int nd_intel_test_cmd_fw_activate_arm(struct nfit_test *t,
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struct nd_intel_fw_activate_arm *nd_cmd,
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unsigned int buf_len, int dimm)
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{
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struct nfit_test_fw *fw = &t->fw[dimm];
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fw->armed = nd_cmd->activate_arm == ND_INTEL_DIMM_FWA_ARM;
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nd_cmd->status = 0;
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return 0;
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}
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static int get_dimm(struct nfit_mem *nfit_mem, unsigned int func)
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{
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@ -1296,6 +1428,14 @@ static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc,
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rc = nd_intel_test_cmd_master_secure_erase(t,
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buf, buf_len, i);
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break;
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case NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO:
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rc = nd_intel_test_cmd_fw_activate_dimminfo(
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t, buf, buf_len, i);
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break;
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case NVDIMM_INTEL_FW_ACTIVATE_ARM:
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rc = nd_intel_test_cmd_fw_activate_arm(
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t, buf, buf_len, i);
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break;
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case ND_INTEL_ENABLE_LSS_STATUS:
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rc = nd_intel_test_cmd_set_lss_status(t,
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buf, buf_len);
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@ -1380,9 +1520,9 @@ static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc,
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if (!nd_desc)
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return -ENOTTY;
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if (cmd == ND_CMD_CALL) {
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if (cmd == ND_CMD_CALL && call_pkg->nd_family
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== NVDIMM_BUS_FAMILY_NFIT) {
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func = call_pkg->nd_command;
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buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
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buf = (void *) call_pkg->nd_payload;
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@ -1406,7 +1546,26 @@ static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc,
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default:
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return -ENOTTY;
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}
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}
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} else if (cmd == ND_CMD_CALL && call_pkg->nd_family
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== NVDIMM_BUS_FAMILY_INTEL) {
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func = call_pkg->nd_command;
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buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
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buf = (void *) call_pkg->nd_payload;
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switch (func) {
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case NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO:
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rc = nvdimm_bus_intel_fw_activate_businfo(t,
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buf, buf_len);
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return rc;
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case NVDIMM_BUS_INTEL_FW_ACTIVATE:
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rc = nvdimm_bus_intel_fw_activate(t, buf,
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buf_len);
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return rc;
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default:
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return -ENOTTY;
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}
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} else if (cmd == ND_CMD_CALL)
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return -ENOTTY;
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if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask))
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return -ENOTTY;
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@ -1832,6 +1991,7 @@ static void nfit_test0_setup(struct nfit_test *t)
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struct acpi_nfit_flush_address *flush;
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struct acpi_nfit_capabilities *pcap;
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unsigned int offset = 0, i;
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unsigned long *acpi_mask;
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/*
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* spa0 (interleave first half of dimm0 and dimm1, note storage
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@ -2558,6 +2718,12 @@ static void nfit_test0_setup(struct nfit_test *t)
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&acpi_desc->dimm_cmd_force_en);
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set_bit(NVDIMM_INTEL_MASTER_SECURE_ERASE,
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&acpi_desc->dimm_cmd_force_en);
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set_bit(NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO, &acpi_desc->dimm_cmd_force_en);
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set_bit(NVDIMM_INTEL_FW_ACTIVATE_ARM, &acpi_desc->dimm_cmd_force_en);
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acpi_mask = &acpi_desc->family_dsm_mask[NVDIMM_BUS_FAMILY_INTEL];
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set_bit(NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO, acpi_mask);
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set_bit(NVDIMM_BUS_INTEL_FW_ACTIVATE, acpi_mask);
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}
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static void nfit_test1_setup(struct nfit_test *t)
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@ -2733,6 +2899,7 @@ static int nfit_ctl_test(struct device *dev)
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struct nd_cmd_clear_error clear_err;
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struct nd_cmd_ars_status ars_stat;
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struct nd_cmd_ars_cap ars_cap;
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struct nd_intel_bus_fw_activate_businfo fwa_info;
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char buf[sizeof(struct nd_cmd_ars_status)
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+ sizeof(struct nd_ars_record)];
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};
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@ -2761,11 +2928,15 @@ static int nfit_ctl_test(struct device *dev)
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.module = THIS_MODULE,
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.provider_name = "ACPI.NFIT",
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.ndctl = acpi_nfit_ctl,
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.bus_family_mask = 1UL << NVDIMM_BUS_FAMILY_NFIT
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| 1UL << NVDIMM_BUS_FAMILY_INTEL,
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},
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.bus_dsm_mask = 1UL << NFIT_CMD_TRANSLATE_SPA
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| 1UL << NFIT_CMD_ARS_INJECT_SET
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| 1UL << NFIT_CMD_ARS_INJECT_CLEAR
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| 1UL << NFIT_CMD_ARS_INJECT_GET,
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.family_dsm_mask[NVDIMM_BUS_FAMILY_INTEL] =
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NVDIMM_BUS_INTEL_FW_ACTIVATE_CMDMASK,
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.dev = &adev->dev,
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};
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@ -2932,6 +3103,36 @@ static int nfit_ctl_test(struct device *dev)
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return -EIO;
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}
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/* test firmware activate bus info */
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cmd_size = sizeof(cmd.fwa_info);
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cmd = (struct nfit_ctl_test_cmd) {
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.pkg = {
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.nd_command = NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO,
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.nd_family = NVDIMM_BUS_FAMILY_INTEL,
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.nd_size_out = cmd_size,
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.nd_fw_size = cmd_size,
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},
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.fwa_info = {
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.state = ND_INTEL_FWA_IDLE,
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.capability = ND_INTEL_BUS_FWA_CAP_FWQUIESCE
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| ND_INTEL_BUS_FWA_CAP_OSQUIESCE,
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.activate_tmo = 1,
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.cpu_quiesce_tmo = 1,
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.io_quiesce_tmo = 1,
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.max_quiesce_tmo = 1,
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},
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};
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rc = setup_result(cmd.buf, cmd_size);
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if (rc)
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return rc;
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rc = acpi_nfit_ctl(&acpi_desc->nd_desc, NULL, ND_CMD_CALL,
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&cmd, sizeof(cmd.pkg) + cmd_size, &cmd_rc);
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if (rc < 0 || cmd_rc) {
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dev_dbg(dev, "%s: failed at: %d rc: %d cmd_rc: %d\n",
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__func__, __LINE__, rc, cmd_rc);
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return -EIO;
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}
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return 0;
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}
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