soc: mediatek: add mt8183 pwrap support
MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>hifive-unleashed-5.1
Hsin-Hsiung Wang
Matthias Brugger
parent
0bd3134d44
commit
919049f6d4
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@ -80,6 +80,8 @@
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#define PWRAP_CAP_BRIDGE BIT(0)
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#define PWRAP_CAP_RESET BIT(1)
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#define PWRAP_CAP_DCM BIT(2)
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#define PWRAP_CAP_INT1_EN BIT(3)
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#define PWRAP_CAP_WDT_SRC1 BIT(4)
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/* defines for slave device wrapper registers */
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enum dew_regs {
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@ -100,6 +102,23 @@ enum dew_regs {
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PWRAP_DEW_CIPHER_EN,
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PWRAP_DEW_RDDMY_NO,
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/* MT6358 only regs */
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PWRAP_SMT_CON1,
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PWRAP_DRV_CON1,
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PWRAP_FILTER_CON0,
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PWRAP_GPIO_PULLEN0_CLR,
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PWRAP_RG_SPI_CON0,
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PWRAP_RG_SPI_RECORD0,
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PWRAP_RG_SPI_CON2,
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PWRAP_RG_SPI_CON3,
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PWRAP_RG_SPI_CON4,
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PWRAP_RG_SPI_CON5,
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PWRAP_RG_SPI_CON6,
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PWRAP_RG_SPI_CON7,
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PWRAP_RG_SPI_CON8,
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PWRAP_RG_SPI_CON13,
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PWRAP_SPISLV_KEY,
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/* MT6397 only regs */
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PWRAP_DEW_EVENT_OUT_EN,
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PWRAP_DEW_EVENT_SRC_EN,
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@ -143,6 +162,34 @@ static const u32 mt6351_regs[] = {
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[PWRAP_DEW_RDDMY_NO] = 0x030C,
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};
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static const u32 mt6358_regs[] = {
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[PWRAP_SMT_CON1] = 0x0030,
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[PWRAP_DRV_CON1] = 0x0038,
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[PWRAP_FILTER_CON0] = 0x0040,
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[PWRAP_GPIO_PULLEN0_CLR] = 0x0098,
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[PWRAP_RG_SPI_CON0] = 0x0408,
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[PWRAP_RG_SPI_RECORD0] = 0x040a,
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[PWRAP_DEW_DIO_EN] = 0x040c,
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[PWRAP_DEW_READ_TEST] = 0x040e,
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[PWRAP_DEW_WRITE_TEST] = 0x0410,
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[PWRAP_DEW_CRC_EN] = 0x0414,
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[PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a,
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[PWRAP_DEW_CIPHER_IV_SEL] = 0x041c,
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[PWRAP_DEW_CIPHER_EN] = 0x041e,
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[PWRAP_DEW_CIPHER_RDY] = 0x0420,
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[PWRAP_DEW_CIPHER_MODE] = 0x0422,
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[PWRAP_DEW_CIPHER_SWRST] = 0x0424,
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[PWRAP_RG_SPI_CON2] = 0x0432,
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[PWRAP_RG_SPI_CON3] = 0x0434,
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[PWRAP_RG_SPI_CON4] = 0x0436,
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[PWRAP_RG_SPI_CON5] = 0x0438,
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[PWRAP_RG_SPI_CON6] = 0x043a,
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[PWRAP_RG_SPI_CON7] = 0x043c,
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[PWRAP_RG_SPI_CON8] = 0x043e,
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[PWRAP_RG_SPI_CON13] = 0x0448,
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[PWRAP_SPISLV_KEY] = 0x044a,
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};
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static const u32 mt6397_regs[] = {
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[PWRAP_DEW_BASE] = 0xbc00,
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[PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
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@ -226,6 +273,8 @@ enum pwrap_regs {
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PWRAP_CIPHER_SWRST,
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PWRAP_DCM_EN,
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PWRAP_DCM_DBC_PRD,
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PWRAP_EINT_STA0_ADR,
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PWRAP_EINT_STA1_ADR,
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/* MT2701 only regs */
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PWRAP_ADC_CMD_ADDR,
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@ -235,8 +284,6 @@ enum pwrap_regs {
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PWRAP_ADC_RDATA_ADDR2,
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/* MT7622 only regs */
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PWRAP_EINT_STA0_ADR,
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PWRAP_EINT_STA1_ADR,
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PWRAP_STA,
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PWRAP_CLR,
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PWRAP_DVFS_ADR8,
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@ -298,6 +345,27 @@ enum pwrap_regs {
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PWRAP_DVFS_WDATA7,
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PWRAP_SPMINF_STA,
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PWRAP_CIPHER_EN,
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/* MT8183 only regs */
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PWRAP_SI_SAMPLE_CTRL,
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PWRAP_CSLEXT_WRITE,
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PWRAP_CSLEXT_READ,
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PWRAP_EXT_CK_WRITE,
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PWRAP_STAUPD_CTRL,
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PWRAP_WACS_P2P_EN,
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PWRAP_INIT_DONE_P2P,
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PWRAP_WACS_MD32_EN,
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PWRAP_INIT_DONE_MD32,
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PWRAP_INT1_EN,
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PWRAP_INT1_FLG,
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PWRAP_INT1_CLR,
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PWRAP_WDT_SRC_EN_1,
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PWRAP_INT_GPS_AUXADC_CMD_ADDR,
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PWRAP_INT_GPS_AUXADC_CMD,
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PWRAP_INT_GPS_AUXADC_RDATA_ADDR,
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PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
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PWRAP_GPSINF_0_STA,
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PWRAP_GPSINF_1_STA,
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};
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static int mt2701_regs[] = {
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@ -686,9 +754,61 @@ static int mt8173_regs[] = {
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[PWRAP_DCM_DBC_PRD] = 0x148,
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};
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static int mt8183_regs[] = {
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[PWRAP_MUX_SEL] = 0x0,
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[PWRAP_WRAP_EN] = 0x4,
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[PWRAP_DIO_EN] = 0x8,
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[PWRAP_SI_SAMPLE_CTRL] = 0xC,
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[PWRAP_RDDMY] = 0x14,
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[PWRAP_CSHEXT_WRITE] = 0x18,
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[PWRAP_CSHEXT_READ] = 0x1C,
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[PWRAP_CSLEXT_WRITE] = 0x20,
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[PWRAP_CSLEXT_READ] = 0x24,
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[PWRAP_EXT_CK_WRITE] = 0x28,
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[PWRAP_STAUPD_CTRL] = 0x30,
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[PWRAP_STAUPD_GRPEN] = 0x34,
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[PWRAP_EINT_STA0_ADR] = 0x38,
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[PWRAP_HARB_HPRIO] = 0x5C,
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[PWRAP_HIPRIO_ARB_EN] = 0x60,
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[PWRAP_MAN_EN] = 0x70,
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[PWRAP_MAN_CMD] = 0x74,
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[PWRAP_WACS0_EN] = 0x80,
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[PWRAP_INIT_DONE0] = 0x84,
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[PWRAP_WACS1_EN] = 0x88,
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[PWRAP_INIT_DONE1] = 0x8C,
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[PWRAP_WACS2_EN] = 0x90,
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[PWRAP_INIT_DONE2] = 0x94,
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[PWRAP_WACS_P2P_EN] = 0xA0,
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[PWRAP_INIT_DONE_P2P] = 0xA4,
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[PWRAP_WACS_MD32_EN] = 0xA8,
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[PWRAP_INIT_DONE_MD32] = 0xAC,
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[PWRAP_INT_EN] = 0xB0,
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[PWRAP_INT_FLG] = 0xB8,
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[PWRAP_INT_CLR] = 0xBC,
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[PWRAP_INT1_EN] = 0xC0,
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[PWRAP_INT1_FLG] = 0xC8,
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[PWRAP_INT1_CLR] = 0xCC,
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[PWRAP_SIG_ADR] = 0xD0,
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[PWRAP_CRC_EN] = 0xE0,
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[PWRAP_TIMER_EN] = 0xE4,
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[PWRAP_WDT_UNIT] = 0xEC,
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[PWRAP_WDT_SRC_EN] = 0xF0,
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[PWRAP_WDT_SRC_EN_1] = 0xF4,
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[PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC,
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[PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0,
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[PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4,
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[PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8,
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[PWRAP_GPSINF_0_STA] = 0x1EC,
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[PWRAP_GPSINF_1_STA] = 0x1F0,
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[PWRAP_WACS2_CMD] = 0xC20,
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[PWRAP_WACS2_RDATA] = 0xC24,
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[PWRAP_WACS2_VLDCLR] = 0xC28,
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};
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enum pmic_type {
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PMIC_MT6323,
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PMIC_MT6351,
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PMIC_MT6358,
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PMIC_MT6380,
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PMIC_MT6397,
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};
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@ -699,6 +819,7 @@ enum pwrap_type {
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PWRAP_MT7622,
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PWRAP_MT8135,
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PWRAP_MT8173,
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PWRAP_MT8183,
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};
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struct pmic_wrapper;
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@ -736,6 +857,7 @@ struct pmic_wrapper_type {
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enum pwrap_type type;
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u32 arb_en_all;
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u32 int_en_all;
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u32 int1_en_all;
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u32 spi_w;
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u32 wdt_src;
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/* Flags indicating the capability for the target pwrap */
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@ -1130,6 +1252,8 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
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case PWRAP_MT7622:
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pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
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break;
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case PWRAP_MT8183:
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break;
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}
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/* Config cipher mode @PMIC */
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@ -1282,6 +1406,23 @@ static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
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return 0;
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}
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static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
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{
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pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
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pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
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pwrap_writel(wrp, 1, PWRAP_CRC_EN);
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pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
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pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
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pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
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pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
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pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
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pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
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return 0;
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}
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static int pwrap_init(struct pmic_wrapper *wrp)
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{
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int ret;
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@ -1368,11 +1509,15 @@ static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
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struct pmic_wrapper *wrp = dev_id;
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rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
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dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
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pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
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if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
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rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
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dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
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pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);
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}
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return IRQ_HANDLED;
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}
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@ -1413,6 +1558,15 @@ static const struct pwrap_slv_type pmic_mt6351 = {
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.pwrap_write = pwrap_write16,
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};
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static const struct pwrap_slv_type pmic_mt6358 = {
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.dew_regs = mt6358_regs,
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.type = PMIC_MT6358,
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.regmap = &pwrap_regmap_config16,
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.caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
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.pwrap_read = pwrap_read16,
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.pwrap_write = pwrap_write16,
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};
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static const struct pwrap_slv_type pmic_mt6380 = {
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.dew_regs = NULL,
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.type = PMIC_MT6380,
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@ -1439,6 +1593,9 @@ static const struct of_device_id of_slave_match_tbl[] = {
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}, {
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.compatible = "mediatek,mt6351",
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.data = &pmic_mt6351,
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}, {
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.compatible = "mediatek,mt6358",
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.data = &pmic_mt6358,
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}, {
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/* The MT6380 PMIC only implements a regulator, so we bind it
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* directly instead of using a MFD.
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@ -1459,6 +1616,7 @@ static const struct pmic_wrapper_type pwrap_mt2701 = {
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.type = PWRAP_MT2701,
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.arb_en_all = 0x3f,
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.int_en_all = ~(u32)(BIT(31) | BIT(2)),
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.int1_en_all = 0,
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.spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
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.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
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.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
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@ -1471,6 +1629,7 @@ static const struct pmic_wrapper_type pwrap_mt6797 = {
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.type = PWRAP_MT6797,
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.arb_en_all = 0x01fff,
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.int_en_all = 0xffffffc6,
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.int1_en_all = 0,
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.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
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.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
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.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
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@ -1483,6 +1642,7 @@ static const struct pmic_wrapper_type pwrap_mt7622 = {
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.type = PWRAP_MT7622,
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.arb_en_all = 0xff,
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.int_en_all = ~(u32)BIT(31),
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.int1_en_all = 0,
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.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
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.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
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.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
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@ -1495,6 +1655,7 @@ static const struct pmic_wrapper_type pwrap_mt8135 = {
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.type = PWRAP_MT8135,
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.arb_en_all = 0x1ff,
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.int_en_all = ~(u32)(BIT(31) | BIT(1)),
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.int1_en_all = 0,
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.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
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.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
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.caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
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@ -1507,6 +1668,7 @@ static const struct pmic_wrapper_type pwrap_mt8173 = {
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.type = PWRAP_MT8173,
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.arb_en_all = 0x3f,
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.int_en_all = ~(u32)(BIT(31) | BIT(1)),
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.int1_en_all = 0,
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.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
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.wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
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.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
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@ -1514,6 +1676,19 @@ static const struct pmic_wrapper_type pwrap_mt8173 = {
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.init_soc_specific = pwrap_mt8173_init_soc_specific,
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};
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static const struct pmic_wrapper_type pwrap_mt8183 = {
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.regs = mt8183_regs,
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.type = PWRAP_MT8183,
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.arb_en_all = 0x3fa75,
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.int_en_all = 0xffffffff,
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.int1_en_all = 0xeef7ffff,
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.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
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.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
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.caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,
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.init_reg_clock = pwrap_common_init_reg_clock,
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.init_soc_specific = pwrap_mt8183_init_soc_specific,
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};
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static const struct of_device_id of_pwrap_match_tbl[] = {
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{
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.compatible = "mediatek,mt2701-pwrap",
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@ -1530,6 +1705,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
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}, {
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.compatible = "mediatek,mt8173-pwrap",
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.data = &pwrap_mt8173,
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}, {
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.compatible = "mediatek,mt8183-pwrap",
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.data = &pwrap_mt8183,
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}, {
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/* sentinel */
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}
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@ -1646,8 +1824,17 @@ static int pwrap_probe(struct platform_device *pdev)
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* so STAUPD of WDT_SRC which should be turned off
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*/
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pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
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if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
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pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
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pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
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pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
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/*
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* We add INT1 interrupt to handle starvation and request exception
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* If we support it, we should enable it here.
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*/
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if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
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pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
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irq = platform_get_irq(pdev, 0);
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ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
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