Merge tag 'drm-intel-next-fixes-2015-09-10' of git://anongit.freedesktop.org/drm-intel into drm-next
Fixes headed for v4.3-rc1, including Maarten's DP MST state checker fix you requested. * tag 'drm-intel-next-fixes-2015-09-10' of git://anongit.freedesktop.org/drm-intel: drm/i915: Allow DSI dual link to be configured on any pipe drm/i915: Don't try to use DDR DVFS on CHV when disabled in the BIOS drm/i915: Fix CSR MMIO address check drm/i915: Limit the number of loops for reading a split 64bit register drm/i915: Fix broken mst get_hw_state. drm/i915: Pass hpd_status_i915[] to intel_get_hpd_pins() in pre-g4x uapi/drm/i915_drm.h: fix userspace compilation. drm/i915: Always mark the object as dirty when used by the GPU
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commit
91b6fc02a2
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@ -1928,6 +1928,8 @@ struct drm_i915_private {
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struct skl_wm_values skl_hw;
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struct vlv_wm_values vlv;
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};
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uint8_t max_level;
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} wm;
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struct i915_runtime_pm pm;
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@ -3383,13 +3385,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
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#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
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#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
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u32 upper, lower, tmp; \
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tmp = I915_READ(upper_reg); \
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u32 upper, lower, old_upper, loop = 0; \
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upper = I915_READ(upper_reg); \
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do { \
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upper = tmp; \
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old_upper = upper; \
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lower = I915_READ(lower_reg); \
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tmp = I915_READ(upper_reg); \
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} while (upper != tmp); \
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upper = I915_READ(upper_reg); \
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} while (upper != old_upper && loop++ < 2); \
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(u64)upper << 32 | lower; })
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#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
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@ -1032,6 +1032,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
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u32 old_read = obj->base.read_domains;
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u32 old_write = obj->base.write_domain;
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obj->dirty = 1; /* be paranoid */
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obj->base.write_domain = obj->base.pending_write_domain;
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if (obj->base.write_domain == 0)
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obj->base.pending_read_domains |= obj->base.read_domains;
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@ -1039,7 +1040,6 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
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i915_vma_move_to_active(vma, req);
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if (obj->base.write_domain) {
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obj->dirty = 1;
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i915_gem_request_assign(&obj->last_write_req, req);
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intel_fb_obj_invalidate(obj, ORIGIN_CS);
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@ -1558,7 +1558,7 @@ static void i9xx_hpd_irq_handler(struct drm_device *dev)
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u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
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intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
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hotplug_trigger, hpd_status_g4x,
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hotplug_trigger, hpd_status_i915,
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i9xx_port_hotplug_long_detect);
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intel_hpd_irq_handler(dev, pin_mask, long_mask);
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}
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@ -350,7 +350,7 @@ static void finish_csr_load(const struct firmware *fw, void *context)
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}
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csr->mmio_count = dmc_header->mmio_count;
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for (i = 0; i < dmc_header->mmio_count; i++) {
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if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE &&
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if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
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dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
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DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
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dmc_header->mmioaddr[i]);
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@ -6305,7 +6305,7 @@ static void intel_connector_check_state(struct intel_connector *connector)
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connector->base.name);
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if (connector->get_hw_state(connector)) {
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struct drm_encoder *encoder = &connector->encoder->base;
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struct intel_encoder *encoder = connector->encoder;
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struct drm_connector_state *conn_state = connector->base.state;
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I915_STATE_WARN(!crtc,
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@ -6317,13 +6317,13 @@ static void intel_connector_check_state(struct intel_connector *connector)
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I915_STATE_WARN(!crtc->state->active,
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"connector is active, but attached crtc isn't\n");
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if (!encoder)
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if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
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return;
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I915_STATE_WARN(conn_state->best_encoder != encoder,
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I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
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"atomic encoder doesn't match attached encoder\n");
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I915_STATE_WARN(conn_state->crtc != encoder->crtc,
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I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
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"attached encoder crtc differs from connector crtc\n");
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} else {
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I915_STATE_WARN(crtc && crtc->state->active,
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@ -173,6 +173,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
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return;
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}
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/* MST encoders are bound to a crtc, not to a connector,
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* force the mapping here for get_hw_state.
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*/
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found->encoder = encoder;
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DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
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intel_mst->port = found->port;
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@ -400,7 +405,7 @@ static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
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static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
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{
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if (connector->encoder) {
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if (connector->encoder && connector->base.state->crtc) {
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enum pipe pipe;
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if (!connector->encoder->get_hw_state(connector->encoder, &pipe))
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return false;
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@ -1048,11 +1048,7 @@ void intel_dsi_init(struct drm_device *dev)
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intel_connector->unregister = intel_connector_unregister;
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/* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
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if (dev_priv->vbt.dsi.config->dual_link) {
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/* XXX: does dual link work on either pipe? */
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intel_encoder->crtc_mask = (1 << PIPE_A);
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intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
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} else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
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if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
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intel_encoder->crtc_mask = (1 << PIPE_A);
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intel_dsi->ports = (1 << PORT_A);
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} else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) {
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@ -1060,6 +1056,9 @@ void intel_dsi_init(struct drm_device *dev)
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intel_dsi->ports = (1 << PORT_C);
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}
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if (dev_priv->vbt.dsi.config->dual_link)
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intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
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/* Create a DSI host (and a device) for each port. */
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for_each_dsi_port(port, intel_dsi->ports) {
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struct intel_dsi_host *host;
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@ -955,8 +955,6 @@ enum vlv_wm_level {
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VLV_WM_LEVEL_PM2,
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VLV_WM_LEVEL_PM5,
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VLV_WM_LEVEL_DDR_DVFS,
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CHV_WM_NUM_LEVELS,
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VLV_WM_NUM_LEVELS = 1,
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};
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/* latency must be in 0.1us units. */
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@ -982,9 +980,13 @@ static void vlv_setup_wm_latency(struct drm_device *dev)
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/* all latencies in usec */
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dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
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dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
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if (IS_CHERRYVIEW(dev_priv)) {
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dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
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dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
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dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
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}
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}
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@ -1137,10 +1139,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
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memset(wm_state, 0, sizeof(*wm_state));
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wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
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if (IS_CHERRYVIEW(dev))
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wm_state->num_levels = CHV_WM_NUM_LEVELS;
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else
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wm_state->num_levels = VLV_WM_NUM_LEVELS;
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wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
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wm_state->num_active_planes = 0;
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@ -1220,7 +1219,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
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}
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/* clear any (partially) filled invalid levels */
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for (level = wm_state->num_levels; level < CHV_WM_NUM_LEVELS; level++) {
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for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
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memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
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memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
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}
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@ -1324,10 +1323,7 @@ static void vlv_merge_wm(struct drm_device *dev,
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struct intel_crtc *crtc;
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int num_active_crtcs = 0;
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if (IS_CHERRYVIEW(dev))
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wm->level = VLV_WM_LEVEL_DDR_DVFS;
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else
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wm->level = VLV_WM_LEVEL_PM2;
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wm->level = to_i915(dev)->wm.max_level;
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wm->cxsr = true;
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for_each_intel_crtc(dev, crtc) {
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@ -4083,9 +4079,29 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
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if (val & DSP_MAXFIFO_PM5_ENABLE)
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wm->level = VLV_WM_LEVEL_PM5;
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/*
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* If DDR DVFS is disabled in the BIOS, Punit
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* will never ack the request. So if that happens
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* assume we don't have to enable/disable DDR DVFS
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* dynamically. To test that just set the REQ_ACK
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* bit to poke the Punit, but don't change the
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* HIGH/LOW bits so that we don't actually change
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* the current state.
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*/
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val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
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if ((val & FORCE_DDR_HIGH_FREQ) == 0)
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wm->level = VLV_WM_LEVEL_DDR_DVFS;
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val |= FORCE_DDR_FREQ_REQ_ACK;
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vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
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if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
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FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
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DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
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"assuming DDR DVFS is disabled\n");
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dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
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} else {
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val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
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if ((val & FORCE_DDR_HIGH_FREQ) == 0)
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wm->level = VLV_WM_LEVEL_DDR_DVFS;
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}
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mutex_unlock(&dev_priv->rps.hw_lock);
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}
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@ -358,7 +358,7 @@ typedef struct drm_i915_irq_wait {
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#define I915_PARAM_HAS_RESOURCE_STREAMER 36
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typedef struct drm_i915_getparam {
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s32 param;
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__s32 param;
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/*
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* WARNING: Using pointers instead of fixed-size u64 means we need to write
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* compat32 code. Don't repeat this mistake.
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