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clk: at91: sama7g5: register cpu clock 

Register CPU clock as being the master clock prescaler. This would
be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
frequencies supported by SAMA7G5 could be directly received from
CPUPLL + master clock prescaler and the extra divider would do no work in
case it would be enabled.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
zero-sugar-mainline-defconfig
Claudiu Beznea 2020-11-19 17:43:17 +02:00 committed by Stephen Boyd
parent 7a110b9107
commit 91f3bf0d53
2 changed files with 7 additions and 7 deletions
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13
drivers/clk/at91/sama7g5.c
View File

@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
if (IS_ERR(regmap))
return;
sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1,
nck(sama7g5_systemck),
nck(sama7g5_periphck),
nck(sama7g5_gck), 8);
@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
}
}
parent_names[0] = md_slck_name;
parent_names[1] = "mainck";
parent_names[2] = "cpupll_divpmcck";
parent_names[3] = "syspll_divpmcck";
hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names,
parent_names[0] = "cpupll_divpmcck";
hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
&mck0_layout, &mck0_characteristics,
&pmc_mck0_lock,
CLK_SET_RATE_PARENT, 0);
if (IS_ERR(hw))
goto err_free;
hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres",
sama7g5_pmc->chws[PMC_CPU] = hw;
hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
&mck0_layout, &mck0_characteristics,
&pmc_mck0_lock, 0);
if (IS_ERR(hw))

1
include/dt-bindings/clock/at91.h
View File

@ -34,6 +34,7 @@
#define PMC_AUDIOPMCPLL (PMC_MAIN + 6)
#define PMC_AUDIOIOPLL (PMC_MAIN + 7)
#define PMC_ETHPLL (PMC_MAIN + 8)
#define PMC_CPU (PMC_MAIN + 9)
#ifndef AT91_PMC_MOSCS
#define AT91_PMC_MOSCS 0 /* MOSCS Flag */