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gpio: sch: Consolidate similar algorithms 

Consolidating similar algorithms into common functions to make
GPIO SCH simpler and manageable.

Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
hifive-unleashed-5.1
Chang Rebecca Swee Fun 2015-01-21 18:32:21 +08:00 committed by Linus Walleij
parent 68d77d5168
commit 920dfd8247
1 changed files with 40 additions and 65 deletions
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105
drivers/gpio/gpio-sch.c
View File

@ -41,7 +41,7 @@ struct sch_gpio {
unsigned short resume_base;
};
#define to_sch_gpio(c) container_of(c, struct sch_gpio, chip)
#define to_sch_gpio(gc) container_of(gc, struct sch_gpio, chip)
static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,
unsigned reg)
@ -63,75 +63,59 @@ static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)
return gpio % 8;
}
static void sch_gpio_enable(struct sch_gpio *sch, unsigned gpio)
{
unsigned short offset, bit;
u8 enable;
spin_lock(&sch->lock);
offset = sch_gpio_offset(sch, gpio, GEN);
bit = sch_gpio_bit(sch, gpio);
enable = inb(sch->iobase + offset);
if (!(enable & (1 << bit)))
outb(enable | (1 << bit), sch->iobase + offset);
spin_unlock(&sch->lock);
}
static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
static int sch_gpio_reg_get(struct gpio_chip *gc, unsigned gpio, unsigned reg)
{
struct sch_gpio *sch = to_sch_gpio(gc);
u8 curr_dirs;
unsigned short offset, bit;
u8 reg_val;
offset = sch_gpio_offset(sch, gpio, reg);
bit = sch_gpio_bit(sch, gpio);
reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
return reg_val;
}
static void sch_gpio_reg_set(struct gpio_chip *gc, unsigned gpio, unsigned reg,
int val)
{
struct sch_gpio *sch = to_sch_gpio(gc);
unsigned short offset, bit;
u8 reg_val;
offset = sch_gpio_offset(sch, gpio, reg);
bit = sch_gpio_bit(sch, gpio);
reg_val = inb(sch->iobase + offset);
if (val)
outb(reg_val | BIT(bit), sch->iobase + offset);
else
outb((reg_val & ~BIT(bit)), sch->iobase + offset);
}
static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
{
struct sch_gpio *sch = to_sch_gpio(gc);
spin_lock(&sch->lock);
offset = sch_gpio_offset(sch, gpio_num, GIO);
bit = sch_gpio_bit(sch, gpio_num);
curr_dirs = inb(sch->iobase + offset);
if (!(curr_dirs & (1 << bit)))
outb(curr_dirs | (1 << bit), sch->iobase + offset);
sch_gpio_reg_set(gc, gpio_num, GIO, 1);
spin_unlock(&sch->lock);
return 0;
}
static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
{
struct sch_gpio *sch = to_sch_gpio(gc);
int res;
unsigned short offset, bit;
offset = sch_gpio_offset(sch, gpio_num, GLV);
bit = sch_gpio_bit(sch, gpio_num);
res = !!(inb(sch->iobase + offset) & (1 << bit));
return res;
return sch_gpio_reg_get(gc, gpio_num, GLV);
}
static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)
{
struct sch_gpio *sch = to_sch_gpio(gc);
u8 curr_vals;
unsigned short offset, bit;
spin_lock(&sch->lock);
offset = sch_gpio_offset(sch, gpio_num, GLV);
bit = sch_gpio_bit(sch, gpio_num);
curr_vals = inb(sch->iobase + offset);
if (val)
outb(curr_vals | (1 << bit), sch->iobase + offset);
else
outb((curr_vals & ~(1 << bit)), sch->iobase + offset);
sch_gpio_reg_set(gc, gpio_num, GLV, val);
spin_unlock(&sch->lock);
}
@ -139,18 +123,9 @@ static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,
int val)
{
struct sch_gpio *sch = to_sch_gpio(gc);
u8 curr_dirs;
unsigned short offset, bit;
spin_lock(&sch->lock);
offset = sch_gpio_offset(sch, gpio_num, GIO);
bit = sch_gpio_bit(sch, gpio_num);
curr_dirs = inb(sch->iobase + offset);
if (curr_dirs & (1 << bit))
outb(curr_dirs & ~(1 << bit), sch->iobase + offset);
sch_gpio_reg_set(gc, gpio_num, GIO, 0);
spin_unlock(&sch->lock);
/*
@ -209,13 +184,13 @@ static int sch_gpio_probe(struct platform_device *pdev)
* GPIO7 is configured by the CMC as SLPIOVR
* Enable GPIO[9:8] core powered gpios explicitly
*/
sch_gpio_enable(sch, 8);
sch_gpio_enable(sch, 9);
sch_gpio_reg_set(&sch->chip, 8, GEN, 1);
sch_gpio_reg_set(&sch->chip, 9, GEN, 1);
/*
* SUS_GPIO[2:0] enabled by default
* Enable SUS_GPIO3 resume powered gpio explicitly
*/
sch_gpio_enable(sch, 13);
sch_gpio_reg_set(&sch->chip, 13, GEN, 1);
break;
case PCI_DEVICE_ID_INTEL_ITC_LPC: