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ARM: gic-v3-its: Add 32bit support to GICv3 ITS 

Wire-up flush_dcache, readq- and writeq-like gic-v3-its assessors, so
GICv3 ITS gets all it needs to be built and run.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
hifive-unleashed-5.1
Vladimir Murzin 2016-11-02 11:54:07 +00:00 committed by Marc Zyngier
parent 0968a61918
commit 92116b804a
1 changed files with 47 additions and 7 deletions
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54
arch/arm/include/asm/arch_gicv3.h
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@ -22,6 +22,7 @@
#include <linux/io.h>
#include <asm/barrier.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1)
@ -230,19 +231,14 @@ static inline void gic_write_bpr1(u32 val)
* AArch32, since the syndrome register doesn't provide any information for
* them.
* Consequently, the following IO helpers use 32bit accesses.
*
* There are only two registers that need 64bit accesses in this driver:
* - GICD_IROUTERn, contain the affinity values associated to each interrupt.
* The upper-word (aff3) will always be 0, so there is no need for a lock.
* - GICR_TYPER is an ID register and doesn't need atomicity.
*/
static inline void gic_write_irouter(u64 val, volatile void __iomem *addr)
static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr)
{
writel_relaxed((u32)val, addr);
writel_relaxed((u32)(val >> 32), addr + 4);
}
static inline u64 gic_read_typer(const volatile void __iomem *addr)
static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
{
u64 val;
@ -251,5 +247,49 @@ static inline u64 gic_read_typer(const volatile void __iomem *addr)
return val;
}
#define gic_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
/*
* GICD_IROUTERn, contain the affinity values associated to each interrupt.
* The upper-word (aff3) will always be 0, so there is no need for a lock.
*/
#define gic_write_irouter(v, c) __gic_writeq_nonatomic(v, c)
/*
* GICR_TYPER is an ID register and doesn't need atomicity.
*/
#define gic_read_typer(c) __gic_readq_nonatomic(c)
/*
* GITS_BASER - hi and lo bits may be accessed independently.
*/
#define gits_read_baser(c) __gic_readq_nonatomic(c)
#define gits_write_baser(v, c) __gic_writeq_nonatomic(v, c)
/*
* GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they
* won't be being used during any updates and can be changed non-atomically
*/
#define gicr_read_propbaser(c) __gic_readq_nonatomic(c)
#define gicr_write_propbaser(v, c) __gic_writeq_nonatomic(v, c)
#define gicr_read_pendbaser(c) __gic_readq_nonatomic(c)
#define gicr_write_pendbaser(v, c) __gic_writeq_nonatomic(v, c)
/*
* GITS_TYPER is an ID register and doesn't need atomicity.
*/
#define gits_read_typer(c) __gic_readq_nonatomic(c)
/*
* GITS_CBASER - hi and lo bits may be accessed independently.
*/
#define gits_read_cbaser(c) __gic_readq_nonatomic(c)
#define gits_write_cbaser(v, c) __gic_writeq_nonatomic(v, c)
/*
* GITS_CWRITER - hi and lo bits may be accessed independently.
*/
#define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c)
#endif /* !__ASSEMBLY__ */
#endif /* !__ASM_ARCH_GICV3_H */