dt-bindings: Add DT binding for PCIE GEN4 EP of the layerscape
Add the documentation for the Device Tree binding of the layerscape PCIe GEN4 controller with EP mode. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>5.4-rM2-2.2.x-imx-squashed
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@ -3,6 +3,8 @@ NXP Layerscape PCIe Gen4 controller
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This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
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the common properties defined in mobiveil-pcie.txt.
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HOST MODE
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=========
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Required properties:
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- compatible: should contain the platform identifier such as:
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"fsl,lx2160a-pcie"
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@ -23,7 +25,20 @@ Required properties:
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- msi-parent : See the generic MSI binding described in
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Documentation/devicetree/bindings/interrupt-controller/msi.txt.
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Example:
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DEVICE MODE
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=========
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Required properties:
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- compatible: should contain the platform identifier such as:
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"fsl,lx2160a-pcie-ep"
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- reg: base addresses and lengths of the PCIe controller register blocks.
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"regs": PCIe controller registers.
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"addr_space" EP device CPU address.
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- apio-wins: number of requested apio outbound windows.
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Optional Property:
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- max-functions: Maximum number of functions that can be configured (default 1).
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RC Example:
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pcie@3400000 {
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compatible = "fsl,lx2160a-pcie";
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@ -50,3 +65,14 @@ Example:
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<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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};
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EP Example:
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pcie_ep@3400000 {
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compatible = "fsl,lx2160a-pcie-ep";
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reg = <0x00 0x03400000 0x0 0x00100000
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0x80 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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apio-wins = <8>;
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status = "disabled";
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};
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