drm/radeon/kms/pm: radeon_set_power_state fixes
- wait for vbl for both profile and dynpm - unify profile and dynpm code paths more - call pm_misc before of after clocks to make sure voltage is changed in the proper order. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -151,6 +151,7 @@ static void radeon_sync_with_vblank(struct radeon_device *rdev)
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static void radeon_set_power_state(struct radeon_device *rdev)
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{
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u32 sclk, mclk;
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bool misc_after = false;
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if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
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(rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
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@ -167,55 +168,47 @@ static void radeon_set_power_state(struct radeon_device *rdev)
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if (mclk > rdev->clock.default_mclk)
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mclk = rdev->clock.default_mclk;
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/* voltage, pcie lanes, etc.*/
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radeon_pm_misc(rdev);
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/* upvolt before raising clocks, downvolt after lowering clocks */
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if (sclk < rdev->pm.current_sclk)
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misc_after = true;
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radeon_sync_with_vblank(rdev);
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if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
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radeon_sync_with_vblank(rdev);
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if (!radeon_pm_in_vbl(rdev))
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return;
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radeon_pm_prepare(rdev);
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/* set engine clock */
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if (sclk != rdev->pm.current_sclk) {
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radeon_pm_debug_check_in_vbl(rdev, false);
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radeon_set_engine_clock(rdev, sclk);
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radeon_pm_debug_check_in_vbl(rdev, true);
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rdev->pm.current_sclk = sclk;
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DRM_DEBUG("Setting: e: %d\n", sclk);
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}
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/* set memory clock */
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if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
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radeon_pm_debug_check_in_vbl(rdev, false);
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radeon_set_memory_clock(rdev, mclk);
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radeon_pm_debug_check_in_vbl(rdev, true);
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rdev->pm.current_mclk = mclk;
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DRM_DEBUG("Setting: m: %d\n", mclk);
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}
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radeon_pm_finish(rdev);
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} else {
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/* set engine clock */
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if (sclk != rdev->pm.current_sclk) {
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radeon_sync_with_vblank(rdev);
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radeon_pm_prepare(rdev);
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radeon_set_engine_clock(rdev, sclk);
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radeon_pm_finish(rdev);
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rdev->pm.current_sclk = sclk;
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DRM_DEBUG("Setting: e: %d\n", sclk);
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}
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/* set memory clock */
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if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
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radeon_sync_with_vblank(rdev);
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radeon_pm_prepare(rdev);
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radeon_set_memory_clock(rdev, mclk);
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radeon_pm_finish(rdev);
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rdev->pm.current_mclk = mclk;
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DRM_DEBUG("Setting: m: %d\n", mclk);
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}
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}
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radeon_pm_prepare(rdev);
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if (!misc_after)
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/* voltage, pcie lanes, etc.*/
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radeon_pm_misc(rdev);
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/* set engine clock */
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if (sclk != rdev->pm.current_sclk) {
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radeon_pm_debug_check_in_vbl(rdev, false);
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radeon_set_engine_clock(rdev, sclk);
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radeon_pm_debug_check_in_vbl(rdev, true);
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rdev->pm.current_sclk = sclk;
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DRM_DEBUG("Setting: e: %d\n", sclk);
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}
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/* set memory clock */
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if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
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radeon_pm_debug_check_in_vbl(rdev, false);
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radeon_set_memory_clock(rdev, mclk);
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radeon_pm_debug_check_in_vbl(rdev, true);
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rdev->pm.current_mclk = mclk;
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DRM_DEBUG("Setting: m: %d\n", mclk);
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}
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if (misc_after)
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/* voltage, pcie lanes, etc.*/
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radeon_pm_misc(rdev);
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radeon_pm_finish(rdev);
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rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
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rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
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} else
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