net/mlx4_core: Capping number of requested MSIXs to MAX_MSIX
We currently manage IRQs in pool_bm which is a bit field of MAX_MSIX bits. Thus, allocating more than MAX_MSIX interrupts can't be managed in pool_bm. Fixing this by capping number of requested MSIXs to MAX_MSIX. Signed-off-by: Matan Barak <matanb@mellanox.com> Signed-off-by: Carol L Soto <clsoto@linux.vnet.ibm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2669,9 +2669,14 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev)
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if (msi_x) {
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int nreq = dev->caps.num_ports * num_online_cpus() + 1;
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bool shared_ports = false;
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nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
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nreq);
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if (nreq > MAX_MSIX) {
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nreq = MAX_MSIX;
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shared_ports = true;
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}
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entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
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if (!entries)
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@ -2694,6 +2699,9 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev)
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bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
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dev->caps.num_ports);
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if (MLX4_IS_LEGACY_EQ_MODE(dev->caps))
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shared_ports = true;
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for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
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if (i == MLX4_EQ_ASYNC)
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continue;
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@ -2701,7 +2709,7 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev)
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priv->eq_table.eq[i].irq =
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entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
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if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
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if (shared_ports) {
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bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
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dev->caps.num_ports);
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/* We don't set affinity hint when there
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