* Add support for hardware-enforced cache coherency on AMD which
obviates the need to flush cachelines before changing the PTE encryption bit, by Krish Sadhukhan. * Add Centaur initialization support for families >= 7, by Tony W Wang-oc. * Add a feature flag for, and expose TSX suspend load tracking feature to KVM, by Cathy Zhang. * Emulate SLDT and STR so that windows programs don't crash on UMIP machines, by Brendan Shanks and Ricardo Neri. * Use the new SERIALIZE insn on Intel hardware which supports it, by Ricardo Neri. * Misc cleanups and fixes. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAl+EKA4ACgkQEsHwGGHe VUq9/RAAtneeyhaM3Erjj+4gLi383ml7n8hlAixZ7x1T5mkV7B5rKtNQ99AYQTbp lbA7qu5mfsEqKeu2WY13IMqHKgfgGXPPUumCTYjgQlC6UoSAMjgtGGCDodqBE8i5 iIq6gp59t4aMn1ltkzNMS0hLGX0i3xA6cBHPB6EVdJhQgaX4oVVs1dL8IbXumj3q NX5qIcaTN/f/IC3EZuCDwZGKUpRF+PWTbD+k02jfhS2crvG/LHJgtisQJ1Eu/ccz yKfiwCBYS7FcuDTxiJDchz1sXD25dgBmBG26voIukSIPbysAPF7O1MULGvKsztFV W/6+VMC+KGUs0ACQHhFl5ALXA73zAJskjzNzRRuduYM0Mr2yAckVet2usicnt/Cp lpmvOpeCjDTPuBQTs0cR9TWjXFeinUkQJOAEcqv9Wh1OKQShZUAJ1jpHwZiDCnhY kzOhq9GAgKNXxcqcTQD8mIap2/GKIppIxAVb7vPxDQfUhUz/60o0eF3cMkeaa216 31Bnf4h+XtJPoJkDOhI8XrPLw6c3KRWP3i3IoBj+raLiylwzzrIczf/7CBgHoIsa fEwuM0PUDVurY38VMRlj1dMFBSFw8U7JqKYyvXKwB3KFeyX7SGZDLmdlvhsRTq20 HJepCVldKZvjDq1zvRFyx/TsZQnoDHsIyv5lAC/EKE3S0/XRg2c= =zXC1 -----END PGP SIGNATURE----- Merge tag 'x86_cpu_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 cpu updates from Borislav Petkov: - Add support for hardware-enforced cache coherency on AMD which obviates the need to flush cachelines before changing the PTE encryption bit (Krish Sadhukhan) - Add Centaur initialization support for families >= 7 (Tony W Wang-oc) - Add a feature flag for, and expose TSX suspend load tracking feature to KVM (Cathy Zhang) - Emulate SLDT and STR so that windows programs don't crash on UMIP machines (Brendan Shanks and Ricardo Neri) - Use the new SERIALIZE insn on Intel hardware which supports it (Ricardo Neri) - Misc cleanups and fixes * tag 'x86_cpu_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domains x86/mm/pat: Don't flush cache if hardware enforces cache coherency across encryption domnains x86/cpu: Add hardware-enforced cache coherency as a CPUID feature x86/cpu/centaur: Add Centaur family >=7 CPUs initialization support x86/cpu/centaur: Replace two-condition switch-case with an if statement x86/kvm: Expose TSX Suspend Load Tracking feature x86/cpufeatures: Enumerate TSX suspend load address tracking instructions x86/umip: Add emulation/spoofing for SLDT and STR instructions x86/cpu: Fix typos and improve the comments in sync_core() x86/cpu: Use XGETBV and XSETBV mnemonics in fpu/internal.h x86/cpu: Use SERIALIZE in sync_core() when available
This commit is contained in:
commit
92a0610b6a
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@ -96,7 +96,7 @@
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#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */
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#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
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#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
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/* free ( 3*32+17) */
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#define X86_FEATURE_SME_COHERENT ( 3*32+17) /* "" AMD hardware-enforced cache coherency */
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#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
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#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
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#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
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@ -368,6 +368,7 @@
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#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
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#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
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#define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */
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#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */
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#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
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#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
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#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
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@ -602,9 +602,7 @@ static inline u64 xgetbv(u32 index)
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{
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u32 eax, edx;
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asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */
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: "=a" (eax), "=d" (edx)
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: "c" (index));
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asm volatile("xgetbv" : "=a" (eax), "=d" (edx) : "c" (index));
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return eax + ((u64)edx << 32);
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}
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@ -613,8 +611,7 @@ static inline void xsetbv(u32 index, u64 value)
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u32 eax = value;
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u32 edx = value >> 32;
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asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */
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: : "a" (eax), "d" (edx), "c" (index));
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asm volatile("xsetbv" :: "a" (eax), "d" (edx), "c" (index));
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}
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#endif /* _ASM_X86_FPU_INTERNAL_H */
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@ -234,6 +234,12 @@ static inline void clwb(volatile void *__p)
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#define nop() asm volatile ("nop")
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static inline void serialize(void)
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{
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/* Instruction opcode for SERIALIZE; supported in binutils >= 2.35. */
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asm volatile(".byte 0xf, 0x1, 0xe8" ::: "memory");
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_SPECIAL_INSNS_H */
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@ -5,6 +5,7 @@
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#include <linux/preempt.h>
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#include <asm/processor.h>
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#include <asm/cpufeature.h>
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#include <asm/special_insns.h>
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#ifdef CONFIG_X86_32
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static inline void iret_to_self(void)
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*
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* b) Text was modified on a different CPU, may subsequently be
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* executed on this CPU, and you want to make sure the new version
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* gets executed. This generally means you're calling this in a IPI.
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* gets executed. This generally means you're calling this in an IPI.
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*
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* If you're calling this for a different reason, you're probably doing
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* it wrong.
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*
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* Like all of Linux's memory ordering operations, this is a
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* compiler barrier as well.
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*/
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static inline void sync_core(void)
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{
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/*
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* There are quite a few ways to do this. IRET-to-self is nice
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* because it works on every CPU, at any CPL (so it's compatible
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* with paravirtualization), and it never exits to a hypervisor.
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* The only down sides are that it's a bit slow (it seems to be
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* a bit more than 2x slower than the fastest options) and that
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* it unmasks NMIs. The "push %cs" is needed because, in
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* paravirtual environments, __KERNEL_CS may not be a valid CS
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* value when we do IRET directly.
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* The SERIALIZE instruction is the most straightforward way to
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* do this, but it is not universally available.
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*/
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if (static_cpu_has(X86_FEATURE_SERIALIZE)) {
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serialize();
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return;
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}
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/*
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* For all other processors, there are quite a few ways to do this.
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* IRET-to-self is nice because it works on every CPU, at any CPL
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* (so it's compatible with paravirtualization), and it never exits
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* to a hypervisor. The only downsides are that it's a bit slow
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* (it seems to be a bit more than 2x slower than the fastest
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* options) and that it unmasks NMIs. The "push %cs" is needed,
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* because in paravirtual environments __KERNEL_CS may not be a
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* valid CS value when we do IRET directly.
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*
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* In case NMI unmasking or performance ever becomes a problem,
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* the next best option appears to be MOV-to-CR2 and an
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* CPUID is the conventional way, but it's nasty: it doesn't
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* exist on some 486-like CPUs, and it usually exits to a
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* hypervisor.
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*
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* Like all of Linux's memory ordering operations, this is a
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* compiler barrier as well.
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*/
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iret_to_self();
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}
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@ -65,6 +65,9 @@ static void init_c3(struct cpuinfo_x86 *c)
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c->x86_cache_alignment = c->x86_clflush_size * 2;
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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}
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if (c->x86 >= 7)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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}
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enum {
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static void early_init_centaur(struct cpuinfo_x86 *c)
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{
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switch (c->x86) {
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#ifdef CONFIG_X86_32
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case 5:
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/* Emulate MTRRs using Centaur's MCR. */
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/* Emulate MTRRs using Centaur's MCR. */
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if (c->x86 == 5)
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set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
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break;
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#endif
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case 6:
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if (c->x86_model >= 0xf)
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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break;
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}
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if ((c->x86 == 6 && c->x86_model >= 0xf) ||
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(c->x86 >= 7))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_SYSENTER32);
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#endif
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set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
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}
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switch (c->x86) {
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#ifdef CONFIG_X86_32
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case 5:
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if (c->x86 == 5) {
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switch (c->x86_model) {
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case 4:
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name = "C6";
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c->x86_cache_size = (cc>>24)+(dd>>24);
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}
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sprintf(c->x86_model_id, "WinChip %s", name);
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break;
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#endif
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case 6:
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init_c3(c);
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break;
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}
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#endif
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if (c->x86 == 6 || c->x86 >= 7)
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init_c3(c);
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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#endif
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{ X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
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{ X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 },
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{ X86_FEATURE_SEV, CPUID_EAX, 1, 0x8000001f, 0 },
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{ X86_FEATURE_SME_COHERENT, CPUID_EAX, 10, 0x8000001f, 0 },
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{ 0, 0, 0, 0, 0 }
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};
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@ -45,11 +45,12 @@
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* value that, lies close to the top of the kernel memory. The limit for the GDT
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* and the IDT are set to zero.
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*
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* Given that SLDT and STR are not commonly used in programs that run on WineHQ
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* or DOSEMU2, they are not emulated.
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*
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* The instruction smsw is emulated to return the value that the register CR0
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* The instruction SMSW is emulated to return the value that the register CR0
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* has at boot time as set in the head_32.
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* SLDT and STR are emulated to return the values that the kernel programmatically
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* assigns:
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* - SLDT returns (GDT_ENTRY_LDT * 8) if an LDT has been set, 0 if not.
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* - STR returns (GDT_ENTRY_TSS * 8).
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*
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* Emulation is provided for both 32-bit and 64-bit processes.
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*
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*data_size += UMIP_GDT_IDT_LIMIT_SIZE;
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memcpy(data, &dummy_limit, UMIP_GDT_IDT_LIMIT_SIZE);
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} else if (umip_inst == UMIP_INST_SMSW) {
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unsigned long dummy_value = CR0_STATE;
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} else if (umip_inst == UMIP_INST_SMSW || umip_inst == UMIP_INST_SLDT ||
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umip_inst == UMIP_INST_STR) {
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unsigned long dummy_value;
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if (umip_inst == UMIP_INST_SMSW) {
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dummy_value = CR0_STATE;
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} else if (umip_inst == UMIP_INST_STR) {
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dummy_value = GDT_ENTRY_TSS * 8;
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} else if (umip_inst == UMIP_INST_SLDT) {
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#ifdef CONFIG_MODIFY_LDT_SYSCALL
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down_read(¤t->mm->context.ldt_usr_sem);
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if (current->mm->context.ldt)
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dummy_value = GDT_ENTRY_LDT * 8;
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else
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dummy_value = 0;
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up_read(¤t->mm->context.ldt_usr_sem);
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#else
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dummy_value = 0;
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#endif
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}
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/*
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* Even though the CR0 register has 4 bytes, the number
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* For these 3 instructions, the number
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* of bytes to be copied in the result buffer is determined
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* by whether the operand is a register or a memory location.
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* If operand is a register, return as many bytes as the operand
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* size. If operand is memory, return only the two least
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* siginificant bytes of CR0.
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* siginificant bytes.
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*/
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if (X86_MODRM_MOD(insn->modrm.value) == 3)
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*data_size = insn->opnd_bytes;
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*data_size = 2;
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memcpy(data, &dummy_value, *data_size);
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/* STR and SLDT are not emulated */
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} else {
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return -EINVAL;
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}
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@ -383,10 +401,6 @@ bool fixup_umip_exception(struct pt_regs *regs)
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umip_pr_warn(regs, "%s instruction cannot be used by applications.\n",
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umip_insns[umip_inst]);
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/* Do not emulate (spoof) SLDT or STR. */
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if (umip_inst == UMIP_INST_STR || umip_inst == UMIP_INST_SLDT)
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return false;
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umip_pr_warn(regs, "For now, expensive software emulation returns the result.\n");
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if (emulate_umip_insn(&insn, umip_inst, dummy_data, &dummy_data_size,
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@ -371,7 +371,7 @@ void kvm_set_cpu_caps(void)
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F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
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F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
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F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
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F(SERIALIZE)
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F(SERIALIZE) | F(TSXLDTRK)
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);
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/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
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@ -384,7 +384,8 @@ static void sev_clflush_pages(struct page *pages[], unsigned long npages)
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uint8_t *page_virtual;
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unsigned long i;
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if (npages == 0 || pages == NULL)
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if (this_cpu_has(X86_FEATURE_SME_COHERENT) || npages == 0 ||
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pages == NULL)
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return;
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for (i = 0; i < npages; i++) {
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@ -1999,7 +1999,7 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc)
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/*
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* Before changing the encryption attribute, we need to flush caches.
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*/
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cpa_flush(&cpa, 1);
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cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT));
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ret = __change_page_attr_set_clr(&cpa, 1);
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Loading…
Reference in a new issue