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drm/nouveau: report channel owner in error messages

Browse source 
Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Marcin Slusarz 2012-12-09 23:00:34 +01:00 committed by Ben Skeggs
parent a2896cede0
commit 93260d3c02
18 changed files with 200 additions and 108 deletions
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6
drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
View file

@ -22,6 +22,7 @@
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <core/client.h>
#include <core/falcon.h> #include <core/falcon.h>
#include <core/class.h> #include <core/class.h>
#include <core/enum.h> #include <core/enum.h>
@ -100,8 +101,9 @@ nva3_copy_intr(struct nouveau_subdev *subdev)
if (stat & 0x00000040) { if (stat & 0x00000040) {
nv_error(falcon, "DISPATCH_ERROR ["); nv_error(falcon, "DISPATCH_ERROR [");
nouveau_enum_print(nva3_copy_isr_error_name, ssta); nouveau_enum_print(nva3_copy_isr_error_name, ssta);
pr_cont("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n", pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
chid, inst << 12, subc, mthd, data); chid, inst << 12, nouveau_client_name(engctx), subc,
mthd, data);
nv_wo32(falcon, 0x004, 0x00000040); nv_wo32(falcon, 0x004, 0x00000040);
stat &= ~0x00000040; stat &= ~0x00000040;
} }

6
drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
View file

@ -22,6 +22,7 @@
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <core/client.h>
#include <core/os.h> #include <core/os.h>
#include <core/enum.h> #include <core/enum.h>
#include <core/class.h> #include <core/class.h>
@ -128,8 +129,9 @@ nv84_crypt_intr(struct nouveau_subdev *subdev)
if (stat) { if (stat) {
nv_error(priv, ""); nv_error(priv, "");
nouveau_bitfield_print(nv84_crypt_intr_mask, stat); nouveau_bitfield_print(nv84_crypt_intr_mask, stat);
pr_cont(" ch %d [0x%010llx] mthd 0x%04x data 0x%08x\n", pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n",
chid, (u64)inst << 12, mthd, data); chid, (u64)inst << 12, nouveau_client_name(engctx),
mthd, data);
} }
nv_wr32(priv, 0x102130, stat); nv_wr32(priv, 0x102130, stat);

6
drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
View file

@ -22,6 +22,7 @@
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <core/client.h>
#include <core/os.h> #include <core/os.h>
#include <core/enum.h> #include <core/enum.h>
#include <core/class.h> #include <core/class.h>
@ -102,8 +103,9 @@ nv98_crypt_intr(struct nouveau_subdev *subdev)
if (stat & 0x00000040) { if (stat & 0x00000040) {
nv_error(priv, "DISPATCH_ERROR ["); nv_error(priv, "DISPATCH_ERROR [");
nouveau_enum_print(nv98_crypt_isr_error_name, ssta); nouveau_enum_print(nv98_crypt_isr_error_name, ssta);
pr_cont("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n", pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
chid, (u64)inst << 12, subc, mthd, data); chid, (u64)inst << 12, nouveau_client_name(engctx),
subc, mthd, data);
nv_wr32(priv, 0x087004, 0x00000040); nv_wr32(priv, 0x087004, 0x00000040);
stat &= ~0x00000040; stat &= ~0x00000040;
} }

22
drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
View file

@ -421,9 +421,12 @@ nv04_fifo_cache_error(struct nouveau_device *device,
} }
if (!nv04_fifo_swmthd(priv, chid, mthd, data)) { if (!nv04_fifo_swmthd(priv, chid, mthd, data)) {
const char *client_name =
nouveau_client_name_for_fifo_chid(&priv->base, chid);
nv_error(priv, nv_error(priv,
"CACHE_ERROR - Ch %d/%d Mthd 0x%04x Data 0x%08x\n", "CACHE_ERROR - ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
chid, (mthd >> 13) & 7, mthd & 0x1ffc, data); chid, client_name, (mthd >> 13) & 7, mthd & 0x1ffc,
data);
} }
nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0); nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
@ -445,11 +448,14 @@ static void
nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv, nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv,
u32 chid) u32 chid)
{ {
const char *client_name;
u32 dma_get = nv_rd32(priv, 0x003244); u32 dma_get = nv_rd32(priv, 0x003244);
u32 dma_put = nv_rd32(priv, 0x003240); u32 dma_put = nv_rd32(priv, 0x003240);
u32 push = nv_rd32(priv, 0x003220); u32 push = nv_rd32(priv, 0x003220);
u32 state = nv_rd32(priv, 0x003228); u32 state = nv_rd32(priv, 0x003228);
client_name = nouveau_client_name_for_fifo_chid(&priv->base, chid);
if (device->card_type == NV_50) { if (device->card_type == NV_50) {
u32 ho_get = nv_rd32(priv, 0x003328); u32 ho_get = nv_rd32(priv, 0x003328);
u32 ho_put = nv_rd32(priv, 0x003320); u32 ho_put = nv_rd32(priv, 0x003320);
@ -457,9 +463,9 @@ nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv,
u32 ib_put = nv_rd32(priv, 0x003330); u32 ib_put = nv_rd32(priv, 0x003330);
nv_error(priv, nv_error(priv,
"DMA_PUSHER - Ch %d Get 0x%02x%08x Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x State 0x%08x (err: %s) Push 0x%08x\n", "DMA_PUSHER - ch %d [%s] get 0x%02x%08x put 0x%02x%08x ib_get 0x%08x ib_put 0x%08x state 0x%08x (err: %s) push 0x%08x\n",
chid, ho_get, dma_get, ho_put, dma_put, ib_get, ib_put, chid, client_name, ho_get, dma_get, ho_put, dma_put,
state, nv_dma_state_err(state), push); ib_get, ib_put, state, nv_dma_state_err(state), push);
/* METHOD_COUNT, in DMA_STATE on earlier chipsets */ /* METHOD_COUNT, in DMA_STATE on earlier chipsets */
nv_wr32(priv, 0x003364, 0x00000000); nv_wr32(priv, 0x003364, 0x00000000);
@ -471,9 +477,9 @@ nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv,
nv_wr32(priv, 0x003334, ib_put); nv_wr32(priv, 0x003334, ib_put);
} else { } else {
nv_error(priv, nv_error(priv,
"DMA_PUSHER - Ch %d Get 0x%08x Put 0x%08x State 0x%08x (err: %s) Push 0x%08x\n", "DMA_PUSHER - ch %d [%s] get 0x%08x put 0x%08x state 0x%08x (err: %s) push 0x%08x\n",
chid, dma_get, dma_put, state, nv_dma_state_err(state), chid, client_name, dma_get, dma_put, state,
push); nv_dma_state_err(state), push);
if (dma_get != dma_put) if (dma_get != dma_put)
nv_wr32(priv, 0x003244, dma_put); nv_wr32(priv, 0x003244, dma_put);

3
drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
View file

@ -129,7 +129,8 @@ nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend,
/* do the kickoff... */ /* do the kickoff... */
nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12); nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) { if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) {
nv_error(priv, "channel %d unload timeout\n", chan->base.chid); nv_error(priv, "channel %d [%s] unload timeout\n",
chan->base.chid, nouveau_client_name(chan));
if (suspend) if (suspend)
ret = -EBUSY; ret = -EBUSY;
} }

3
drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
View file

@ -100,7 +100,8 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff); done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff);
nv_wr32(priv, 0x002520, save); nv_wr32(priv, 0x002520, save);
if (!done) { if (!done) {
nv_error(priv, "channel %d unload timeout\n", chan->base.chid); nv_error(priv, "channel %d [%s] unload timeout\n",
chan->base.chid, nouveau_client_name(chan));
if (suspend) if (suspend)
return -EBUSY; return -EBUSY;
} }

42
drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
View file

@ -149,7 +149,8 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
nv_wr32(priv, 0x002634, chan->base.chid); nv_wr32(priv, 0x002634, chan->base.chid);
if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
nv_error(priv, "channel %d kick timeout\n", chan->base.chid); nv_error(priv, "channel %d [%s] kick timeout\n",
chan->base.chid, nouveau_client_name(chan));
if (suspend) if (suspend)
return -EBUSY; return -EBUSY;
} }
@ -333,17 +334,17 @@ nvc0_fifo_cclass = {
******************************************************************************/ ******************************************************************************/
static const struct nouveau_enum nvc0_fifo_fault_unit[] = { static const struct nouveau_enum nvc0_fifo_fault_unit[] = {
{ 0x00, "PGRAPH" }, { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
{ 0x03, "PEEPHOLE" }, { 0x03, "PEEPHOLE" },
{ 0x04, "BAR1" }, { 0x04, "BAR1" },
{ 0x05, "BAR3" }, { 0x05, "BAR3" },
{ 0x07, "PFIFO" }, { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
{ 0x10, "PBSP" }, { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP },
{ 0x11, "PPPP" }, { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x13, "PCOUNTER" }, { 0x13, "PCOUNTER" },
{ 0x14, "PVP" }, { 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
{ 0x15, "PCOPY0" }, { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 },
{ 0x16, "PCOPY1" }, { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 },
{ 0x17, "PDAEMON" }, { 0x17, "PDAEMON" },
{} {}
}; };
@ -402,6 +403,9 @@ nvc0_fifo_isr_vm_fault(struct nvc0_fifo_priv *priv, int unit)
u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10)); u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10)); u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
u32 client = (stat & 0x00001f00) >> 8; u32 client = (stat & 0x00001f00) >> 8;
const struct nouveau_enum *en;
struct nouveau_engine *engine;
struct nouveau_object *engctx = NULL;
switch (unit) { switch (unit) {
case 3: /* PEEPHOLE */ case 3: /* PEEPHOLE */
@ -421,7 +425,7 @@ nvc0_fifo_isr_vm_fault(struct nvc0_fifo_priv *priv, int unit)
"write" : "read", (u64)vahi << 32 | valo); "write" : "read", (u64)vahi << 32 | valo);
nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f); nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);
pr_cont("] from "); pr_cont("] from ");
nouveau_enum_print(nvc0_fifo_fault_unit, unit); en = nouveau_enum_print(nvc0_fifo_fault_unit, unit);
if (stat & 0x00000040) { if (stat & 0x00000040) {
pr_cont("/"); pr_cont("/");
nouveau_enum_print(nvc0_fifo_fault_hubclient, client); nouveau_enum_print(nvc0_fifo_fault_hubclient, client);
@ -429,7 +433,17 @@ nvc0_fifo_isr_vm_fault(struct nvc0_fifo_priv *priv, int unit)
pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24); pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24);
nouveau_enum_print(nvc0_fifo_fault_gpcclient, client); nouveau_enum_print(nvc0_fifo_fault_gpcclient, client);
} }
pr_cont(" on channel 0x%010llx\n", (u64)inst << 12);
if (en && en->data2) {
engine = nouveau_engine(priv, en->data2);
if (engine)
engctx = nouveau_engctx_get(engine, inst);
}
pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12,
nouveau_client_name(engctx));
nouveau_engctx_put(engctx);
} }
static int static int
@ -485,9 +499,11 @@ nvc0_fifo_isr_subfifo_intr(struct nvc0_fifo_priv *priv, int unit)
nv_error(priv, "SUBFIFO%d:", unit); nv_error(priv, "SUBFIFO%d:", unit);
nouveau_bitfield_print(nvc0_fifo_subfifo_intr, show); nouveau_bitfield_print(nvc0_fifo_subfifo_intr, show);
pr_cont("\n"); pr_cont("\n");
nv_error(priv, "SUBFIFO%d: ch %d subc %d mthd 0x%04x " nv_error(priv,
"data 0x%08x\n", "SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
unit, chid, subc, mthd, data); unit, chid,
nouveau_client_name_for_fifo_chid(&priv->base, chid),
subc, mthd, data);
} }
nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);

29
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
View file

@ -184,7 +184,8 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
nv_wr32(priv, 0x002634, chan->base.chid); nv_wr32(priv, 0x002634, chan->base.chid);
if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
nv_error(priv, "channel %d kick timeout\n", chan->base.chid); nv_error(priv, "channel %d [%s] kick timeout\n",
chan->base.chid, nouveau_client_name(chan));
if (suspend) if (suspend)
return -EBUSY; return -EBUSY;
} }
@ -412,12 +413,15 @@ nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit)
u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10)); u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10));
u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10)); u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10));
u32 client = (stat & 0x00001f00) >> 8; u32 client = (stat & 0x00001f00) >> 8;
const struct nouveau_enum *en;
struct nouveau_engine *engine;
struct nouveau_object *engctx = NULL;
nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ? nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ?
"write" : "read", (u64)vahi << 32 | valo); "write" : "read", (u64)vahi << 32 | valo);
nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f); nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f);
pr_cont("] from "); pr_cont("] from ");
nouveau_enum_print(nve0_fifo_fault_unit, unit); en = nouveau_enum_print(nve0_fifo_fault_unit, unit);
if (stat & 0x00000040) { if (stat & 0x00000040) {
pr_cont("/"); pr_cont("/");
nouveau_enum_print(nve0_fifo_fault_hubclient, client); nouveau_enum_print(nve0_fifo_fault_hubclient, client);
@ -425,7 +429,18 @@ nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit)
pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24); pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24);
nouveau_enum_print(nve0_fifo_fault_gpcclient, client); nouveau_enum_print(nve0_fifo_fault_gpcclient, client);
} }
pr_cont(" on channel 0x%010llx\n", (u64)inst << 12);
if (en && en->data2) {
engine = nouveau_engine(priv, en->data2);
if (engine)
engctx = nouveau_engctx_get(engine, inst);
}
pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12,
nouveau_client_name(engctx));
nouveau_engctx_put(engctx);
} }
static int static int
@ -481,9 +496,11 @@ nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit)
nv_error(priv, "SUBFIFO%d:", unit); nv_error(priv, "SUBFIFO%d:", unit);
nouveau_bitfield_print(nve0_fifo_subfifo_intr, show); nouveau_bitfield_print(nve0_fifo_subfifo_intr, show);
pr_cont("\n"); pr_cont("\n");
nv_error(priv, "SUBFIFO%d: ch %d subc %d mthd 0x%04x " nv_error(priv,
"data 0x%08x\n", "SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
unit, chid, subc, mthd, data); unit, chid,
nouveau_client_name_for_fifo_chid(&priv->base, chid),
subc, mthd, data);
} }
nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);

8
drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
View file

@ -22,6 +22,7 @@
* DEALINGS IN THE SOFTWARE. * DEALINGS IN THE SOFTWARE.
*/ */
#include <core/client.h>
#include <core/os.h> #include <core/os.h>
#include <core/class.h> #include <core/class.h>
#include <core/handle.h> #include <core/handle.h>
@ -1304,9 +1305,10 @@ nv04_graph_intr(struct nouveau_subdev *subdev)
pr_cont(" nstatus:"); pr_cont(" nstatus:");
nouveau_bitfield_print(nv04_graph_nstatus, nstatus); nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
pr_cont("\n"); pr_cont("\n");
nv_error(priv, "ch %d/%d class 0x%04x " nv_error(priv,
"mthd 0x%04x data 0x%08x\n", "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, subc, class, mthd, data); chid, nouveau_client_name(chan), subc, class, mthd,
data);
} }
nouveau_namedb_put(handle); nouveau_namedb_put(handle);

8
drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
View file

@ -22,6 +22,7 @@
* DEALINGS IN THE SOFTWARE. * DEALINGS IN THE SOFTWARE.
*/ */
#include <core/client.h>
#include <core/os.h> #include <core/os.h>
#include <core/class.h> #include <core/class.h>
#include <core/handle.h> #include <core/handle.h>
@ -1200,9 +1201,10 @@ nv10_graph_intr(struct nouveau_subdev *subdev)
pr_cont(" nstatus:"); pr_cont(" nstatus:");
nouveau_bitfield_print(nv10_graph_nstatus, nstatus); nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
pr_cont("\n"); pr_cont("\n");
nv_error(priv, "ch %d/%d class 0x%04x " nv_error(priv,
"mthd 0x%04x data 0x%08x\n", "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, subc, class, mthd, data); chid, nouveau_client_name(chan), subc, class, mthd,
data);
} }
nouveau_namedb_put(handle); nouveau_namedb_put(handle);

7
drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
View file

@ -1,3 +1,4 @@
#include <core/client.h>
#include <core/os.h> #include <core/os.h>
#include <core/class.h> #include <core/class.h>
#include <core/engctx.h> #include <core/engctx.h>
@ -231,8 +232,10 @@ nv20_graph_intr(struct nouveau_subdev *subdev)
pr_cont(" nstatus:"); pr_cont(" nstatus:");
nouveau_bitfield_print(nv10_graph_nstatus, nstatus); nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
pr_cont("\n"); pr_cont("\n");
nv_error(priv, "ch %d/%d class 0x%04x mthd 0x%04x data 0x%08x\n", nv_error(priv,
chid, subc, class, mthd, data); "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, nouveau_client_name(engctx), subc, class, mthd,
data);
} }
nouveau_engctx_put(engctx); nouveau_engctx_put(engctx);

8
drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
View file

@ -22,6 +22,7 @@
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <core/client.h>
#include <core/os.h> #include <core/os.h>
#include <core/class.h> #include <core/class.h>
#include <core/handle.h> #include <core/handle.h>
@ -328,9 +329,10 @@ nv40_graph_intr(struct nouveau_subdev *subdev)
pr_cont(" nstatus:"); pr_cont(" nstatus:");
nouveau_bitfield_print(nv10_graph_nstatus, nstatus); nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
pr_cont("\n"); pr_cont("\n");
nv_error(priv, "ch %d [0x%08x] subc %d class 0x%04x " nv_error(priv,
"mthd 0x%04x data 0x%08x\n", "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 4, subc, class, mthd, data); chid, inst << 4, nouveau_client_name(engctx), subc,
class, mthd, data);
} }
nouveau_engctx_put(engctx); nouveau_engctx_put(engctx);

34
drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
View file

@ -24,6 +24,7 @@
#include <core/os.h> #include <core/os.h>
#include <core/class.h> #include <core/class.h>
#include <core/client.h>
#include <core/handle.h> #include <core/handle.h>
#include <core/engctx.h> #include <core/engctx.h>
#include <core/enum.h> #include <core/enum.h>
@ -532,7 +533,7 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old,
static int static int
nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
int chid, u64 inst) int chid, u64 inst, struct nouveau_object *engctx)
{ {
u32 status = nv_rd32(priv, 0x400108); u32 status = nv_rd32(priv, 0x400108);
u32 ustatus; u32 ustatus;
@ -565,12 +566,11 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
nv_error(priv, "TRAP DISPATCH_FAULT\n"); nv_error(priv, "TRAP DISPATCH_FAULT\n");
if (display && (addr & 0x80000000)) { if (display && (addr & 0x80000000)) {
nv_error(priv, "ch %d [0x%010llx] " nv_error(priv,
"subc %d class 0x%04x mthd 0x%04x " "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n",
"data 0x%08x%08x " chid, inst,
"400808 0x%08x 400848 0x%08x\n", nouveau_client_name(engctx), subc,
chid, inst, subc, class, mthd, datah, class, mthd, datah, datal, addr, r848);
datal, addr, r848);
} else } else
if (display) { if (display) {
nv_error(priv, "no stuck command?\n"); nv_error(priv, "no stuck command?\n");
@ -591,11 +591,11 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
nv_error(priv, "TRAP DISPATCH_QUERY\n"); nv_error(priv, "TRAP DISPATCH_QUERY\n");
if (display && (addr & 0x80000000)) { if (display && (addr & 0x80000000)) {
nv_error(priv, "ch %d [0x%010llx] " nv_error(priv,
"subc %d class 0x%04x mthd 0x%04x " "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n",
"data 0x%08x 40084c 0x%08x\n", chid, inst,
chid, inst, subc, class, mthd, nouveau_client_name(engctx), subc,
data, addr); class, mthd, data, addr);
} else } else
if (display) { if (display) {
nv_error(priv, "no stuck command?\n"); nv_error(priv, "no stuck command?\n");
@ -778,7 +778,8 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
} }
if (stat & 0x00200000) { if (stat & 0x00200000) {
if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12)) if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12,
engctx))
show &= ~0x00200000; show &= ~0x00200000;
} }
@ -789,9 +790,10 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
nv_error(priv, ""); nv_error(priv, "");
nouveau_bitfield_print(nv50_graph_intr_name, show); nouveau_bitfield_print(nv50_graph_intr_name, show);
pr_cont("\n"); pr_cont("\n");
nv_error(priv, "ch %d [0x%010llx] subc %d class 0x%04x " nv_error(priv,
"mthd 0x%04x data 0x%08x\n", "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, (u64)inst << 12, subc, class, mthd, data); chid, (u64)inst << 12, nouveau_client_name(engctx),
subc, class, mthd, data);
} }
if (nv_rd32(priv, 0x400824) & (1 << 31)) if (nv_rd32(priv, 0x400824) & (1 << 31))

24
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
View file

@ -433,10 +433,10 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
if (stat & 0x00000010) { if (stat & 0x00000010) {
handle = nouveau_handle_get_class(engctx, class); handle = nouveau_handle_get_class(engctx, class);
if (!handle || nv_call(handle->object, mthd, data)) { if (!handle || nv_call(handle->object, mthd, data)) {
nv_error(priv, "ILLEGAL_MTHD ch %d [0x%010llx] " nv_error(priv,
"subc %d class 0x%04x mthd 0x%04x " "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
"data 0x%08x\n", chid, inst << 12, nouveau_client_name(engctx),
chid, inst << 12, subc, class, mthd, data); subc, class, mthd, data);
} }
nouveau_handle_put(handle); nouveau_handle_put(handle);
nv_wr32(priv, 0x400100, 0x00000010); nv_wr32(priv, 0x400100, 0x00000010);
@ -444,9 +444,10 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
} }
if (stat & 0x00000020) { if (stat & 0x00000020) {
nv_error(priv, "ILLEGAL_CLASS ch %d [0x%010llx] subc %d " nv_error(priv,
"class 0x%04x mthd 0x%04x data 0x%08x\n", "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst << 12, subc, class, mthd, data); chid, inst << 12, nouveau_client_name(engctx), subc,
class, mthd, data);
nv_wr32(priv, 0x400100, 0x00000020); nv_wr32(priv, 0x400100, 0x00000020);
stat &= ~0x00000020; stat &= ~0x00000020;
} }
@ -454,15 +455,16 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
if (stat & 0x00100000) { if (stat & 0x00100000) {
nv_error(priv, "DATA_ERROR ["); nv_error(priv, "DATA_ERROR [");
nouveau_enum_print(nv50_data_error_names, code); nouveau_enum_print(nv50_data_error_names, code);
pr_cont("] ch %d [0x%010llx] subc %d class 0x%04x " pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
"mthd 0x%04x data 0x%08x\n", chid, inst << 12, nouveau_client_name(engctx), subc,
chid, inst << 12, subc, class, mthd, data); class, mthd, data);
nv_wr32(priv, 0x400100, 0x00100000); nv_wr32(priv, 0x400100, 0x00100000);
stat &= ~0x00100000; stat &= ~0x00100000;
} }
if (stat & 0x00200000) { if (stat & 0x00200000) {
nv_error(priv, "TRAP ch %d [0x%010llx]\n", chid, inst << 12); nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
nouveau_client_name(engctx));
nvc0_graph_trap_intr(priv); nvc0_graph_trap_intr(priv);
nv_wr32(priv, 0x400100, 0x00200000); nv_wr32(priv, 0x400100, 0x00200000);
stat &= ~0x00200000; stat &= ~0x00200000;

44
drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
View file

@ -78,15 +78,16 @@ nve0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
} }
static void static void
nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst) nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst,
struct nouveau_object *engctx)
{ {
u32 trap = nv_rd32(priv, 0x400108); u32 trap = nv_rd32(priv, 0x400108);
int rop; int rop;
if (trap & 0x00000001) { if (trap & 0x00000001) {
u32 stat = nv_rd32(priv, 0x404000); u32 stat = nv_rd32(priv, 0x404000);
nv_error(priv, "DISPATCH ch %d [0x%010llx] 0x%08x\n", nv_error(priv, "DISPATCH ch %d [0x%010llx %s] 0x%08x\n",
chid, inst, stat); chid, inst, nouveau_client_name(engctx), stat);
nv_wr32(priv, 0x404000, 0xc0000000); nv_wr32(priv, 0x404000, 0xc0000000);
nv_wr32(priv, 0x400108, 0x00000001); nv_wr32(priv, 0x400108, 0x00000001);
trap &= ~0x00000001; trap &= ~0x00000001;
@ -94,8 +95,8 @@ nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst)
if (trap & 0x00000010) { if (trap & 0x00000010) {
u32 stat = nv_rd32(priv, 0x405840); u32 stat = nv_rd32(priv, 0x405840);
nv_error(priv, "SHADER ch %d [0x%010llx] 0x%08x\n", nv_error(priv, "SHADER ch %d [0x%010llx %s] 0x%08x\n",
chid, inst, stat); chid, inst, nouveau_client_name(engctx), stat);
nv_wr32(priv, 0x405840, 0xc0000000); nv_wr32(priv, 0x405840, 0xc0000000);
nv_wr32(priv, 0x400108, 0x00000010); nv_wr32(priv, 0x400108, 0x00000010);
trap &= ~0x00000010; trap &= ~0x00000010;
@ -105,8 +106,10 @@ nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst)
for (rop = 0; rop < priv->rop_nr; rop++) { for (rop = 0; rop < priv->rop_nr; rop++) {
u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070)); u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070));
u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144)); u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144));
nv_error(priv, "ROP%d ch %d [0x%010llx] 0x%08x 0x%08x\n", nv_error(priv,
rop, chid, inst, statz, statc); "ROP%d ch %d [0x%010llx %s] 0x%08x 0x%08x\n",
rop, chid, inst, nouveau_client_name(engctx),
statz, statc);
nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
} }
@ -115,8 +118,8 @@ nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst)
} }
if (trap) { if (trap) {
nv_error(priv, "TRAP ch %d [0x%010llx] 0x%08x\n", nv_error(priv, "TRAP ch %d [0x%010llx %s] 0x%08x\n",
chid, inst, trap); chid, inst, nouveau_client_name(engctx), trap);
nv_wr32(priv, 0x400108, trap); nv_wr32(priv, 0x400108, trap);
} }
} }
@ -145,10 +148,10 @@ nve0_graph_intr(struct nouveau_subdev *subdev)
if (stat & 0x00000010) { if (stat & 0x00000010) {
handle = nouveau_handle_get_class(engctx, class); handle = nouveau_handle_get_class(engctx, class);
if (!handle || nv_call(handle->object, mthd, data)) { if (!handle || nv_call(handle->object, mthd, data)) {
nv_error(priv, "ILLEGAL_MTHD ch %d [0x%010llx] " nv_error(priv,
"subc %d class 0x%04x mthd 0x%04x " "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
"data 0x%08x\n", chid, inst, nouveau_client_name(engctx), subc,
chid, inst, subc, class, mthd, data); class, mthd, data);
} }
nouveau_handle_put(handle); nouveau_handle_put(handle);
nv_wr32(priv, 0x400100, 0x00000010); nv_wr32(priv, 0x400100, 0x00000010);
@ -156,9 +159,10 @@ nve0_graph_intr(struct nouveau_subdev *subdev)
} }
if (stat & 0x00000020) { if (stat & 0x00000020) {
nv_error(priv, "ILLEGAL_CLASS ch %d [0x%010llx] subc %d " nv_error(priv,
"class 0x%04x mthd 0x%04x data 0x%08x\n", "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, inst, subc, class, mthd, data); chid, inst, nouveau_client_name(engctx), subc, class,
mthd, data);
nv_wr32(priv, 0x400100, 0x00000020); nv_wr32(priv, 0x400100, 0x00000020);
stat &= ~0x00000020; stat &= ~0x00000020;
} }
@ -166,15 +170,15 @@ nve0_graph_intr(struct nouveau_subdev *subdev)
if (stat & 0x00100000) { if (stat & 0x00100000) {
nv_error(priv, "DATA_ERROR ["); nv_error(priv, "DATA_ERROR [");
nouveau_enum_print(nv50_data_error_names, code); nouveau_enum_print(nv50_data_error_names, code);
pr_cont("] ch %d [0x%010llx] subc %d class 0x%04x " pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
"mthd 0x%04x data 0x%08x\n", chid, inst, nouveau_client_name(engctx), subc, class,
chid, inst, subc, class, mthd, data); mthd, data);
nv_wr32(priv, 0x400100, 0x00100000); nv_wr32(priv, 0x400100, 0x00100000);
stat &= ~0x00100000; stat &= ~0x00100000;
} }
if (stat & 0x00200000) { if (stat & 0x00200000) {
nve0_graph_trap_isr(priv, chid, inst); nve0_graph_trap_isr(priv, chid, inst, engctx);
nv_wr32(priv, 0x400100, 0x00200000); nv_wr32(priv, 0x400100, 0x00200000);
stat &= ~0x00200000; stat &= ~0x00200000;
} }

7
drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
View file

@ -22,6 +22,7 @@
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <core/client.h>
#include <core/os.h> #include <core/os.h>
#include <core/class.h> #include <core/class.h>
#include <core/engctx.h> #include <core/engctx.h>
@ -231,8 +232,10 @@ nv31_mpeg_intr(struct nouveau_subdev *subdev)
nv_wr32(priv, 0x00b230, 0x00000001); nv_wr32(priv, 0x00b230, 0x00000001);
if (show) { if (show) {
nv_error(priv, "ch %d [0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n", nv_error(priv,
chid, inst << 4, stat, type, mthd, data); "ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
chid, inst << 4, nouveau_client_name(engctx), stat,
type, mthd, data);
} }
nouveau_engctx_put(engctx); nouveau_engctx_put(engctx);

48
drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
View file

@ -22,8 +22,10 @@
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <core/object.h> #include <core/client.h>
#include <core/enum.h> #include <core/enum.h>
#include <core/engctx.h>
#include <core/object.h>
#include <subdev/fb.h> #include <subdev/fb.h>
#include <subdev/bios.h> #include <subdev/bios.h>
@ -302,17 +304,18 @@ static const struct nouveau_enum vm_client[] = {
}; };
static const struct nouveau_enum vm_engine[] = { static const struct nouveau_enum vm_engine[] = {
{ 0x00000000, "PGRAPH", NULL }, { 0x00000000, "PGRAPH", NULL, NVDEV_ENGINE_GR },
{ 0x00000001, "PVP", NULL }, { 0x00000001, "PVP", NULL, NVDEV_ENGINE_VP },
{ 0x00000004, "PEEPHOLE", NULL }, { 0x00000004, "PEEPHOLE", NULL },
{ 0x00000005, "PFIFO", vm_pfifo_subclients }, { 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO },
{ 0x00000006, "BAR", vm_bar_subclients }, { 0x00000006, "BAR", vm_bar_subclients },
{ 0x00000008, "PPPP", NULL }, { 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP },
{ 0x00000009, "PBSP", NULL }, { 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
{ 0x0000000a, "PCRYPT", NULL }, { 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
{ 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CRYPT },
{ 0x0000000b, "PCOUNTER", NULL }, { 0x0000000b, "PCOUNTER", NULL },
{ 0x0000000c, "SEMAPHORE_BG", NULL }, { 0x0000000c, "SEMAPHORE_BG", NULL },
{ 0x0000000d, "PCOPY", NULL }, { 0x0000000d, "PCOPY", NULL, NVDEV_ENGINE_COPY0 },
{ 0x0000000e, "PDAEMON", NULL }, { 0x0000000e, "PDAEMON", NULL },
{} {}
}; };
@ -334,8 +337,10 @@ static void
nv50_fb_intr(struct nouveau_subdev *subdev) nv50_fb_intr(struct nouveau_subdev *subdev)
{ {
struct nouveau_device *device = nv_device(subdev); struct nouveau_device *device = nv_device(subdev);
struct nouveau_engine *engine;
struct nv50_fb_priv *priv = (void *)subdev; struct nv50_fb_priv *priv = (void *)subdev;
const struct nouveau_enum *en, *cl; const struct nouveau_enum *en, *cl;
struct nouveau_object *engctx = NULL;
u32 trap[6], idx, chan; u32 trap[6], idx, chan;
u8 st0, st1, st2, st3; u8 st0, st1, st2, st3;
int i; int i;
@ -366,11 +371,30 @@ nv50_fb_intr(struct nouveau_subdev *subdev)
} }
chan = (trap[2] << 16) | trap[1]; chan = (trap[2] << 16) | trap[1];
nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x ",
(trap[5] & 0x00000100) ? "read" : "write",
trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan);
en = nouveau_enum_find(vm_engine, st0); en = nouveau_enum_find(vm_engine, st0);
if (en && en->data2) {
const struct nouveau_enum *orig_en = en;
while (en->name && en->value == st0 && en->data2) {
engine = nouveau_engine(subdev, en->data2);
if (engine) {
engctx = nouveau_engctx_get(engine, chan);
if (engctx)
break;
}
en++;
}
if (!engctx)
en = orig_en;
}
nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ",
(trap[5] & 0x00000100) ? "read" : "write",
trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan,
nouveau_client_name(engctx));
nouveau_engctx_put(engctx);
if (en) if (en)
pr_cont("%s/", en->name); pr_cont("%s/", en->name);
else else

3
drivers/gpu/drm/nouveau/nouveau_chan.c
View file

@ -58,7 +58,8 @@ nouveau_channel_idle(struct nouveau_channel *chan)
} }
if (ret) if (ret)
NV_ERROR(cli, "failed to idle channel 0x%08x\n", chan->handle); NV_ERROR(cli, "failed to idle channel 0x%08x [%s]\n",
chan->handle, cli->base.name);
return ret; return ret;
} }