x86, apic: Move SGI UV functionality out of generic IO-APIC code
Move UV specific functionality out of the generic IO-APIC code. Signed-off-by: Dimitri Sivanich <sivanich@sgi.com> LKML-Reference: <20091013203236.GD20543@sgi.com> [ Cleaned up the code some more in their new places. ] Signed-off-by: Ingo Molnar <mingo@elte.hu>hifive-unleashed-5.1
Dimitri Sivanich
Ingo Molnar
parent
6c2c502910
commit
9338ad6ffb
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@ -79,14 +79,31 @@ static inline void set_io_apic_irq_attr(struct io_apic_irq_attr *irq_attr,
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int ioapic, int ioapic_pin,
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int trigger, int polarity)
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{
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irq_attr->ioapic = ioapic;
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irq_attr->ioapic_pin = ioapic_pin;
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irq_attr->trigger = trigger;
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irq_attr->polarity = polarity;
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irq_attr->ioapic = ioapic;
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irq_attr->ioapic_pin = ioapic_pin;
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irq_attr->trigger = trigger;
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irq_attr->polarity = polarity;
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}
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extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin,
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struct io_apic_irq_attr *irq_attr);
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/*
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* This is performance-critical, we want to do it O(1)
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*
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* Most irqs are mapped 1:1 with pins.
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*/
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struct irq_cfg {
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struct irq_pin_list *irq_2_pin;
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cpumask_var_t domain;
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cpumask_var_t old_domain;
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unsigned move_cleanup_count;
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u8 vector;
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u8 move_in_progress : 1;
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};
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extern struct irq_cfg *irq_cfg(unsigned int);
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extern int assign_irq_vector(int, struct irq_cfg *, const struct cpumask *);
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extern void send_cleanup_vector(struct irq_cfg *);
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extern unsigned int set_desc_affinity(struct irq_desc *, const struct cpumask *);
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extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin, struct io_apic_irq_attr *irq_attr);
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extern void setup_ioapic_dest(void);
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extern void enable_IO_APIC(void);
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@ -31,13 +31,6 @@ enum {
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UV_AFFINITY_CPU
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};
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extern struct irq_chip uv_irq_chip;
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extern int
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arch_enable_uv_irq(char *, unsigned int, int, int, unsigned long, int);
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extern void arch_disable_uv_irq(int, unsigned long);
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extern int uv_set_irq_affinity(unsigned int, const struct cpumask *);
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extern int uv_irq_2_mmr_info(int, unsigned long *, int *);
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extern int uv_setup_irq(char *, int, int, unsigned long, int);
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extern void uv_teardown_irq(unsigned int);
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@ -60,8 +60,6 @@
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#include <asm/irq_remapping.h>
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#include <asm/hpet.h>
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#include <asm/hw_irq.h>
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#include <asm/uv/uv_hub.h>
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#include <asm/uv/uv_irq.h>
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#include <asm/apic.h>
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@ -140,20 +138,6 @@ static struct irq_pin_list *get_one_free_irq_2_pin(int node)
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return pin;
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}
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/*
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* This is performance-critical, we want to do it O(1)
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*
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* Most irqs are mapped 1:1 with pins.
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*/
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struct irq_cfg {
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struct irq_pin_list *irq_2_pin;
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cpumask_var_t domain;
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cpumask_var_t old_domain;
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unsigned move_cleanup_count;
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u8 vector;
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u8 move_in_progress : 1;
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};
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/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
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#ifdef CONFIG_SPARSE_IRQ
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static struct irq_cfg irq_cfgx[] = {
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@ -209,7 +193,7 @@ int __init arch_early_irq_init(void)
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}
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#ifdef CONFIG_SPARSE_IRQ
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static struct irq_cfg *irq_cfg(unsigned int irq)
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struct irq_cfg *irq_cfg(unsigned int irq)
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{
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struct irq_cfg *cfg = NULL;
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struct irq_desc *desc;
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@ -361,7 +345,7 @@ void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
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/* end for move_irq_desc */
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#else
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static struct irq_cfg *irq_cfg(unsigned int irq)
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struct irq_cfg *irq_cfg(unsigned int irq)
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{
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return irq < nr_irqs ? irq_cfgx + irq : NULL;
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}
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@ -1237,8 +1221,7 @@ next:
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return err;
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}
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static int
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assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
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int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
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{
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int err;
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unsigned long flags;
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@ -2245,7 +2228,7 @@ static int ioapic_retrigger_irq(unsigned int irq)
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*/
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#ifdef CONFIG_SMP
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static void send_cleanup_vector(struct irq_cfg *cfg)
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void send_cleanup_vector(struct irq_cfg *cfg)
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{
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cpumask_var_t cleanup_mask;
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@ -2289,15 +2272,12 @@ static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq
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}
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}
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static int
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assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
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/*
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* Either sets desc->affinity to a valid value, and returns
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* ->cpu_mask_to_apicid of that, or returns BAD_APICID and
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* leaves desc->affinity untouched.
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*/
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static unsigned int
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unsigned int
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set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
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{
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struct irq_cfg *cfg;
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@ -3725,116 +3705,6 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
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}
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#endif /* CONFIG_HT_IRQ */
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#ifdef CONFIG_X86_UV
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/*
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* Re-target the irq to the specified CPU and enable the specified MMR located
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* on the specified blade to allow the sending of MSIs to the specified CPU.
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*/
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int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
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unsigned long mmr_offset, int restrict)
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{
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const struct cpumask *eligible_cpu = cpumask_of(cpu);
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struct irq_desc *desc = irq_to_desc(irq);
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struct irq_cfg *cfg;
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int mmr_pnode;
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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unsigned long flags;
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int err;
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BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
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cfg = irq_cfg(irq);
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err = assign_irq_vector(irq, cfg, eligible_cpu);
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if (err != 0)
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return err;
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if (restrict == UV_AFFINITY_CPU)
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desc->status |= IRQ_NO_BALANCING;
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else
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desc->status |= IRQ_MOVE_PCNTXT;
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spin_lock_irqsave(&vector_lock, flags);
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set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
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irq_name);
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spin_unlock_irqrestore(&vector_lock, flags);
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->vector = cfg->vector;
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entry->delivery_mode = apic->irq_delivery_mode;
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entry->dest_mode = apic->irq_dest_mode;
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entry->polarity = 0;
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entry->trigger = 0;
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entry->mask = 0;
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entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
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mmr_pnode = uv_blade_to_pnode(mmr_blade);
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uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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return irq;
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}
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/*
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* Disable the specified MMR located on the specified blade so that MSIs are
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* longer allowed to be sent.
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*/
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void arch_disable_uv_irq(int mmr_pnode, unsigned long mmr_offset)
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{
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->mask = 1;
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uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
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}
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int uv_set_irq_affinity(unsigned int irq, const struct cpumask *mask)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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struct irq_cfg *cfg = desc->chip_data;
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unsigned int dest;
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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unsigned long mmr_offset;
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unsigned mmr_pnode;
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dest = set_desc_affinity(desc, mask);
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if (dest == BAD_APICID)
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return -1;
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->vector = cfg->vector;
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entry->delivery_mode = apic->irq_delivery_mode;
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entry->dest_mode = apic->irq_dest_mode;
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entry->polarity = 0;
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entry->trigger = 0;
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entry->mask = 0;
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entry->dest = dest;
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/* Get previously stored MMR and pnode of hub sourcing interrupts */
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if (uv_irq_2_mmr_info(irq, &mmr_offset, &mmr_pnode))
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return -1;
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uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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return 0;
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}
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#endif /* CONFIG_X86_64 */
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int __init io_apic_get_redir_entries (int ioapic)
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{
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union IO_APIC_reg_01 reg_01;
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@ -18,13 +18,16 @@
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/* MMR offset and pnode of hub sourcing interrupts for a given irq */
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struct uv_irq_2_mmr_pnode{
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struct rb_node list;
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unsigned long offset;
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int pnode;
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int irq;
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struct rb_node list;
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unsigned long offset;
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int pnode;
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int irq;
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};
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static spinlock_t uv_irq_lock;
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static struct rb_root uv_irq_root;
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static spinlock_t uv_irq_lock;
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static struct rb_root uv_irq_root;
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static int uv_set_irq_affinity(unsigned int, const struct cpumask *);
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static void uv_noop(unsigned int irq)
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{
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@ -131,6 +134,114 @@ int uv_irq_2_mmr_info(int irq, unsigned long *offset, int *pnode)
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return -1;
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}
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/*
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* Re-target the irq to the specified CPU and enable the specified MMR located
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* on the specified blade to allow the sending of MSIs to the specified CPU.
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*/
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static int
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arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
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unsigned long mmr_offset, int restrict)
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{
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const struct cpumask *eligible_cpu = cpumask_of(cpu);
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struct irq_desc *desc = irq_to_desc(irq);
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struct irq_cfg *cfg;
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int mmr_pnode;
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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int err;
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BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
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sizeof(unsigned long));
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cfg = irq_cfg(irq);
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err = assign_irq_vector(irq, cfg, eligible_cpu);
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if (err != 0)
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return err;
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if (restrict == UV_AFFINITY_CPU)
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desc->status |= IRQ_NO_BALANCING;
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else
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desc->status |= IRQ_MOVE_PCNTXT;
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set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
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irq_name);
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->vector = cfg->vector;
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entry->delivery_mode = apic->irq_delivery_mode;
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entry->dest_mode = apic->irq_dest_mode;
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entry->polarity = 0;
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entry->trigger = 0;
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entry->mask = 0;
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entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
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mmr_pnode = uv_blade_to_pnode(mmr_blade);
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uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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return irq;
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}
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/*
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* Disable the specified MMR located on the specified blade so that MSIs are
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* longer allowed to be sent.
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*/
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static void arch_disable_uv_irq(int mmr_pnode, unsigned long mmr_offset)
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{
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
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sizeof(unsigned long));
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->mask = 1;
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uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
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}
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static int uv_set_irq_affinity(unsigned int irq, const struct cpumask *mask)
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{
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struct irq_desc *desc = irq_to_desc(irq);
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struct irq_cfg *cfg = desc->chip_data;
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unsigned int dest;
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unsigned long mmr_value;
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struct uv_IO_APIC_route_entry *entry;
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unsigned long mmr_offset;
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unsigned mmr_pnode;
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dest = set_desc_affinity(desc, mask);
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if (dest == BAD_APICID)
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return -1;
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mmr_value = 0;
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entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
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entry->vector = cfg->vector;
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entry->delivery_mode = apic->irq_delivery_mode;
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entry->dest_mode = apic->irq_dest_mode;
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entry->polarity = 0;
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entry->trigger = 0;
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entry->mask = 0;
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entry->dest = dest;
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/* Get previously stored MMR and pnode of hub sourcing interrupts */
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if (uv_irq_2_mmr_info(irq, &mmr_offset, &mmr_pnode))
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return -1;
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uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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return 0;
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}
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/*
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* Set up a mapping of an available irq and vector, and enable the specified
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* MMR that defines the MSI that is to be sent to the specified CPU when an
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