dmaengine: dw: Don't pollute CTL_LO on iDMA 32-bit
Intel iDMA 32-bit doesn't have a concept of bus masters and thus there is no need to setup any kind of masters in the CTL_LO register. Moreover, the burst size for memory-to-memory transfer is not what is says, we need to have a corrected list of possible sizes. Note, that the size of 8 items, each of that up to 4 bytes, is chosen because of maximum of 1/2 FIFO, which is 64 bytes on Intel Merrifield. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>hifive-unleashed-5.1
Andy Shevchenko
Vinod Koul
parent
91f0ff883e
commit
934891b0a1
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@ -37,27 +37,6 @@
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* support descriptor writeback.
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*/
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#define DWC_DEFAULT_CTLLO(_chan) ({ \
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struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
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struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
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bool _is_slave = is_slave_direction(_dwc->direction); \
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u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
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DW_DMA_MSIZE_16; \
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u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
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DW_DMA_MSIZE_16; \
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u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ? \
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_dwc->dws.p_master : _dwc->dws.m_master; \
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u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ? \
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_dwc->dws.p_master : _dwc->dws.m_master; \
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\
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(DWC_CTLL_DST_MSIZE(_dmsize) \
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| DWC_CTLL_SRC_MSIZE(_smsize) \
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| DWC_CTLL_LLP_D_EN \
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| DWC_CTLL_LLP_S_EN \
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| DWC_CTLL_DMS(_dms) \
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| DWC_CTLL_SMS(_sms)); \
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})
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/* The set of bus widths supported by the DMA controller */
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#define DW_DMA_BUSWIDTHS \
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BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
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@ -596,7 +575,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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src_width = dst_width = __ffs(data_width | src | dest | len);
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ctllo = DWC_DEFAULT_CTLLO(chan)
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ctllo = dw->prepare_ctllo(dwc)
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| DWC_CTLL_DST_WIDTH(dst_width)
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| DWC_CTLL_SRC_WIDTH(src_width)
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| DWC_CTLL_DST_INC
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@ -676,10 +655,10 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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case DMA_MEM_TO_DEV:
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reg_width = __ffs(sconfig->dst_addr_width);
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reg = sconfig->dst_addr;
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ctllo = (DWC_DEFAULT_CTLLO(chan)
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ctllo = dw->prepare_ctllo(dwc)
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| DWC_CTLL_DST_WIDTH(reg_width)
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| DWC_CTLL_DST_FIX
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| DWC_CTLL_SRC_INC);
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| DWC_CTLL_SRC_INC;
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ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
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DWC_CTLL_FC(DW_DMA_FC_D_M2P);
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@ -726,10 +705,10 @@ slave_sg_todev_fill_desc:
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case DMA_DEV_TO_MEM:
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reg_width = __ffs(sconfig->src_addr_width);
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reg = sconfig->src_addr;
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ctllo = (DWC_DEFAULT_CTLLO(chan)
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ctllo = dw->prepare_ctllo(dwc)
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| DWC_CTLL_SRC_WIDTH(reg_width)
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| DWC_CTLL_DST_INC
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| DWC_CTLL_SRC_FIX);
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| DWC_CTLL_SRC_FIX;
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ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
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DWC_CTLL_FC(DW_DMA_FC_D_P2M);
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@ -4,6 +4,7 @@
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// Copyright (C) 2013,2018 Intel Corporation
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#include <linux/bitops.h>
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#include <linux/dmaengine.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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@ -63,6 +64,22 @@ static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
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return DWC_CTLH_BLOCK_TS(block) << width;
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}
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static u32 dw_dma_prepare_ctllo(struct dw_dma_chan *dwc)
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{
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struct dma_slave_config *sconfig = &dwc->dma_sconfig;
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bool is_slave = is_slave_direction(dwc->direction);
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u8 smsize = is_slave ? sconfig->src_maxburst : DW_DMA_MSIZE_16;
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u8 dmsize = is_slave ? sconfig->dst_maxburst : DW_DMA_MSIZE_16;
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u8 p_master = dwc->dws.p_master;
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u8 m_master = dwc->dws.m_master;
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u8 dms = (dwc->direction == DMA_MEM_TO_DEV) ? p_master : m_master;
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u8 sms = (dwc->direction == DMA_DEV_TO_MEM) ? p_master : m_master;
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return DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN |
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DWC_CTLL_DST_MSIZE(dmsize) | DWC_CTLL_SRC_MSIZE(smsize) |
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DWC_CTLL_DMS(dms) | DWC_CTLL_SMS(sms);
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}
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static void dw_dma_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
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{
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/*
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@ -99,6 +116,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)
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dw->initialize_chan = dw_dma_initialize_chan;
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dw->suspend_chan = dw_dma_suspend_chan;
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dw->resume_chan = dw_dma_resume_chan;
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dw->prepare_ctllo = dw_dma_prepare_ctllo;
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dw->encode_maxburst = dw_dma_encode_maxburst;
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dw->bytes2block = dw_dma_bytes2block;
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dw->block2bytes = dw_dma_block2bytes;
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@ -2,6 +2,7 @@
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// Copyright (C) 2013,2018 Intel Corporation
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#include <linux/bitops.h>
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#include <linux/dmaengine.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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@ -69,6 +70,17 @@ static size_t idma32_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
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return IDMA32C_CTLH_BLOCK_TS(block);
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}
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static u32 idma32_prepare_ctllo(struct dw_dma_chan *dwc)
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{
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struct dma_slave_config *sconfig = &dwc->dma_sconfig;
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bool is_slave = is_slave_direction(dwc->direction);
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u8 smsize = is_slave ? sconfig->src_maxburst : IDMA32_MSIZE_8;
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u8 dmsize = is_slave ? sconfig->dst_maxburst : IDMA32_MSIZE_8;
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return DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN |
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DWC_CTLL_DST_MSIZE(dmsize) | DWC_CTLL_SRC_MSIZE(smsize);
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}
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static void idma32_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
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{
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*maxburst = *maxburst > 1 ? fls(*maxburst) - 1 : 0;
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@ -126,6 +138,7 @@ int idma32_dma_probe(struct dw_dma_chip *chip)
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dw->initialize_chan = idma32_initialize_chan;
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dw->suspend_chan = idma32_suspend_chan;
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dw->resume_chan = idma32_resume_chan;
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dw->prepare_ctllo = idma32_prepare_ctllo;
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dw->encode_maxburst = idma32_encode_maxburst;
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dw->bytes2block = idma32_bytes2block;
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dw->block2bytes = idma32_block2bytes;
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@ -222,6 +222,16 @@ enum dw_dma_msize {
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/* iDMA 32-bit support */
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/* bursts size */
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enum idma32_msize {
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IDMA32_MSIZE_1,
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IDMA32_MSIZE_2,
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IDMA32_MSIZE_4,
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IDMA32_MSIZE_8,
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IDMA32_MSIZE_16,
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IDMA32_MSIZE_32,
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};
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/* Bitfields in CTL_HI */
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#define IDMA32C_CTLH_BLOCK_TS_MASK GENMASK(16, 0)
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#define IDMA32C_CTLH_BLOCK_TS(x) ((x) & IDMA32C_CTLH_BLOCK_TS_MASK)
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@ -316,6 +326,7 @@ struct dw_dma {
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void (*initialize_chan)(struct dw_dma_chan *dwc);
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void (*suspend_chan)(struct dw_dma_chan *dwc, bool drain);
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void (*resume_chan)(struct dw_dma_chan *dwc, bool drain);
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u32 (*prepare_ctllo)(struct dw_dma_chan *dwc);
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void (*encode_maxburst)(struct dw_dma_chan *dwc, u32 *maxburst);
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u32 (*bytes2block)(struct dw_dma_chan *dwc, size_t bytes,
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unsigned int width, size_t *len);
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