IB/ipath: Use S_ABORT not cancel and abort on exit freeze mode after recovery
This centralizes the use of the abort functionality, removes the unneeded buffer cancel (abort does the same thing), sets up to ignore launch errors after abort, same as cancel. We need abort on exit from freeze mode to avoid having buffers stuck in the busy state, if a user process happened to complete the send while we were in freeze mode doing the recovery. Signed-off-by: Dave Olson <dave.olson@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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@ -706,9 +706,9 @@ void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
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u64 sendctrl, sendorig;
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ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
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sendorig = dd->ipath_sendctrl | INFINIPATH_S_DISARM;
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sendorig = dd->ipath_sendctrl;
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for (i = first; i < last; i++) {
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sendctrl = sendorig |
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sendctrl = sendorig | INFINIPATH_S_DISARM |
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(i << INFINIPATH_S_DISARMPIOBUF_SHIFT);
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ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
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sendctrl);
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@ -719,12 +719,12 @@ void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
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* while we were looping; no critical bits that would require
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* locking.
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*
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* Write a 0, and then the original value, reading scratch in
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* disable PIOAVAILUPD, then re-enable, reading scratch in
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* between. This seems to avoid a chip timing race that causes
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* pioavail updates to memory to stop.
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*/
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ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
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0);
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sendorig & ~IPATH_S_PIOBUFAVAILUPD);
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sendorig = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
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ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
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dd->ipath_sendctrl);
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@ -1596,6 +1596,35 @@ int ipath_waitfor_mdio_cmdready(struct ipath_devdata *dd)
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return ret;
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}
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/*
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* Flush all sends that might be in the ready to send state, as well as any
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* that are in the process of being sent. Used whenever we need to be
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* sure the send side is idle. Cleans up all buffer state by canceling
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* all pio buffers, and issuing an abort, which cleans up anything in the
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* launch fifo. The cancel is superfluous on some chip versions, but
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* it's safer to always do it.
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* PIOAvail bits are updated by the chip as if normal send had happened.
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*/
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void ipath_cancel_sends(struct ipath_devdata *dd)
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{
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ipath_dbg("Cancelling all in-progress send buffers\n");
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dd->ipath_lastcancel = jiffies+HZ/2; /* skip armlaunch errs a bit */
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/*
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* the abort bit is auto-clearing. We read scratch to be sure
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* that cancels and the abort have taken effect in the chip.
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*/
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ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
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INFINIPATH_S_ABORT);
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ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
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ipath_disarm_piobufs(dd, 0,
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(unsigned)(dd->ipath_piobcnt2k + dd->ipath_piobcnt4k));
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/* and again, be sure all have hit the chip */
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ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
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}
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static void ipath_set_ib_lstate(struct ipath_devdata *dd, int which)
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{
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static const char *what[4] = {
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@ -1617,14 +1646,8 @@ static void ipath_set_ib_lstate(struct ipath_devdata *dd, int which)
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INFINIPATH_IBCS_LINKTRAININGSTATE_MASK]);
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/* flush all queued sends when going to DOWN or INIT, to be sure that
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* they don't block MAD packets */
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if (!linkcmd || linkcmd == INFINIPATH_IBCC_LINKCMD_INIT) {
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ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
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INFINIPATH_S_ABORT);
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ipath_disarm_piobufs(dd, dd->ipath_lastport_piobuf,
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(unsigned)(dd->ipath_piobcnt2k +
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dd->ipath_piobcnt4k) -
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dd->ipath_lastport_piobuf);
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}
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if (!linkcmd || linkcmd == INFINIPATH_IBCC_LINKCMD_INIT)
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ipath_cancel_sends(dd);
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ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
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dd->ipath_ibcctrl | which);
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@ -1967,17 +1990,9 @@ void ipath_shutdown_device(struct ipath_devdata *dd)
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*/
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udelay(5);
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/*
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* abort any armed or launched PIO buffers that didn't go. (self
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* clearing). Will cause any packet currently being transmitted to
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* go out with an EBP, and may also cause a short packet error on
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* the receiver.
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*/
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ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
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INFINIPATH_S_ABORT);
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ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
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INFINIPATH_IBCC_LINKINITCMD_SHIFT);
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ipath_cancel_sends(dd);
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/* disable IBC */
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dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
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@ -509,6 +509,13 @@ static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
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if (!hwerrs) {
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ipath_dbg("Clearing freezemode on ignored or "
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"recovered hardware error\n");
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/*
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* clear all sends, becauase they have may been
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* completed by usercode while in freeze mode, and
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* therefore would not be sent, and eventually
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* might cause the process to run out of bufs
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*/
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ipath_cancel_sends(dd);
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ctrl &= ~INFINIPATH_C_FREEZEMODE;
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ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
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ctrl);
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@ -1566,11 +1573,6 @@ static int ipath_ht_early_init(struct ipath_devdata *dd)
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writel(16, piobuf);
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piobuf += pioincr;
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}
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/*
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* self-clearing
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*/
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ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
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INFINIPATH_S_ABORT);
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ipath_get_eeprom_info(dd);
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if (dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
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@ -1599,7 +1601,6 @@ static int ipath_ht_txe_recover(struct ipath_devdata *dd)
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}
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dev_info(&dd->pcidev->dev,
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"Recovering from TXE PIO parity error\n");
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ipath_disarm_senderrbufs(dd, 1);
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return 1;
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}
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@ -430,8 +430,19 @@ static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
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*dd->ipath_statusp |= IPATH_STATUS_HWERROR;
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dd->ipath_flags &= ~IPATH_INITTED;
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} else {
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ipath_dbg("Clearing freezemode on ignored hardware "
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"error\n");
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static u32 freeze_cnt;
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freeze_cnt++;
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ipath_dbg("Clearing freezemode on ignored or recovered "
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"hardware error (%u)\n", freeze_cnt);
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/*
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* clear all sends, becauase they have may been
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* completed by usercode while in freeze mode, and
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* therefore would not be sent, and eventually
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* might cause the process to run out of bufs
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*/
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ipath_cancel_sends(dd);
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ctrl &= ~INFINIPATH_C_FREEZEMODE;
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ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
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dd->ipath_control);
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}
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@ -1371,7 +1382,6 @@ static int ipath_pe_txe_recover(struct ipath_devdata *dd)
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dev_info(&dd->pcidev->dev,
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"Recovering from TXE PIO parity error\n");
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}
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ipath_disarm_senderrbufs(dd, 1);
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return 1;
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}
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@ -777,6 +777,12 @@ int ipath_init_chip(struct ipath_devdata *dd, int reinit)
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piobufs, dd->ipath_pbufsport, uports);
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dd->ipath_f_early_init(dd);
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/*
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* cancel any possible active sends from early driver load.
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* Follows early_init because some chips have to initialize
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* PIO buffers in early_init to avoid false parity errors.
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*/
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ipath_cancel_sends(dd);
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/* early_init sets rcvhdrentsize and rcvhdrsize, so this must be
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* done after early_init */
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@ -93,7 +93,8 @@ void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite)
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if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) {
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int i;
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if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG)) {
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if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG) &&
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dd->ipath_lastcancel > jiffies) {
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__IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG,
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"SendbufErrs %lx %lx", sbuf[0],
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sbuf[1]);
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@ -108,7 +109,8 @@ void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite)
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ipath_clrpiobuf(dd, i);
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ipath_disarm_piobufs(dd, i, 1);
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}
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dd->ipath_lastcancel = jiffies+3; /* no armlaunch for a bit */
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/* ignore armlaunch errs for a bit */
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dd->ipath_lastcancel = jiffies+3;
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}
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}
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* Flush all queued sends when link went to DOWN or INIT,
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* to be sure that they don't block SMA and other MAD packets
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*/
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ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
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INFINIPATH_S_ABORT);
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ipath_disarm_piobufs(dd, dd->ipath_lastport_piobuf,
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(unsigned)(dd->ipath_piobcnt2k +
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dd->ipath_piobcnt4k) -
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dd->ipath_lastport_piobuf);
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ipath_cancel_sends(dd);
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}
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else if (lstate == IPATH_IBSTATE_INIT || lstate == IPATH_IBSTATE_ARM ||
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lstate == IPATH_IBSTATE_ACTIVE) {
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@ -676,6 +676,7 @@ int ipath_unordered_wc(void);
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void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first,
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unsigned cnt);
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void ipath_cancel_sends(struct ipath_devdata *);
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int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *);
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void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *);
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