drm/radeon: fix eDP clk and lane setup for scaled modes
Need to use the adjusted mode since we are sending native timing and using the scaler for non-native modes. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> cc: stable@vger.kernel.org
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@ -340,7 +340,7 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
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((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
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((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
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(radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
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(radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
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struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
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struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
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radeon_dp_set_link_config(connector, mode);
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radeon_dp_set_link_config(connector, adjusted_mode);
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}
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}
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return true;
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return true;
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