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MLK-23252-1 clk: imx8mp: Add DISP2 pixel clock 

This patch adds DISP2 pixel clock for the second instance of LCDIFv3
in the MEDIAMIX subsystem.

Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Liu Ying 2019-10-16 13:22:25 +08:00
parent 6036be3457
commit 93bdb13365
2 changed files with 7 additions and 1 deletions
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5
drivers/clk/imx/clk-imx8mp.c
View File

@ -212,6 +212,10 @@ static const char *imx8mp_mipi_dsi_esc_rx_sels[] = {"osc_24m", "sys_pll2_100m",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
"clk_ext3", "audio_pll2_out", };
static const char *imx8mp_media_disp2_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
"audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m",
"sys_pll3_out", "clk_ext4", };
static const char *imx8mp_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
"sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
"audio_pll1_out", "sys_pll1_266m", };
@ -679,6 +683,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
clks[IMX8MP_CLK_AHB] = imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000);
clks[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mp_audio_ahb_sels, base + 0x9100);
clks[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_composite("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, base + 0x9200);
clks[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_composite("media_disp2_pix", imx8mp_media_disp2_pix_sels, base + 0x9300);
/* IPG */
clks[IMX8MP_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1);

3
include/dt-bindings/clock/imx8mp-clock.h
View File

@ -299,8 +299,9 @@
#define IMX8MP_CLK_DRAM_CORE 286
#define IMX8MP_CLK_ARM 287
#define IMX8MP_CLK_A53_CORE 288
#define IMX8MP_CLK_MEDIA_DISP2_PIX 289
#define IMX8MP_CLK_END 289
#define IMX8MP_CLK_END 290
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1