[ARM] 4815/1: RealView: Add clockevents suport for the local timers
This patch registers the local timers on ARM11MPCore as clock event devices. The clock device can be set up as periodic or oneshot. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>hifive-unleashed-5.1
Catalin Marinas
Russell King
parent
a8655e83fc
commit
93c2904d50
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@ -16,8 +16,8 @@
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#include <linux/jiffies.h>
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#include <linux/percpu.h>
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#include <linux/clockchips.h>
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#include <linux/irq.h>
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#include <asm/mach/time.h>
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#include <asm/hardware/arm_twd.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware.h>
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@ -43,6 +43,43 @@ void local_timer_interrupt(void)
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static unsigned long mpcore_timer_rate;
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static void local_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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void __iomem *base = TWD_BASE(smp_processor_id());
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unsigned long ctrl;
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switch(mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* timer load already set up */
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ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
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| TWD_TIMER_CONTROL_PERIODIC;
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* period set, and timer enabled in 'next_event' hook */
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ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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ctrl = 0;
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}
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__raw_writel(ctrl, base + TWD_TIMER_CONTROL);
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}
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static int local_timer_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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void __iomem *base = TWD_BASE(smp_processor_id());
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unsigned long ctrl = __raw_readl(base + TWD_TIMER_CONTROL);
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__raw_writel(evt, base + TWD_TIMER_COUNTER);
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__raw_writel(ctrl | TWD_TIMER_CONTROL_ENABLE, base + TWD_TIMER_CONTROL);
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return 0;
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}
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/*
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* local_timer_ack: checks for a local timer interrupt.
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*
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@ -61,12 +98,11 @@ int local_timer_ack(void)
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return 0;
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}
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void __cpuinit local_timer_setup(unsigned int cpu)
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static void __cpuinit twd_calibrate_rate(unsigned int cpu)
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{
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void __iomem *base = TWD_BASE(cpu);
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unsigned int load, offset;
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unsigned long load, count;
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u64 waitjiffies;
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unsigned int count;
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/*
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* If this is the first time round, we need to work out how fast
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@ -104,36 +140,36 @@ void __cpuinit local_timer_setup(unsigned int cpu)
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load = mpcore_timer_rate / HZ;
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__raw_writel(load, base + TWD_TIMER_LOAD);
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__raw_writel(0x7, base + TWD_TIMER_CONTROL);
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}
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/*
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* Now maneuver our local tick into the right part of the jiffy.
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* Start by working out where within the tick our local timer
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* interrupt should go.
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*/
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offset = ((mpcore_timer_rate / HZ) / (NR_CPUS + 1)) * (cpu + 1);
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/*
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* Setup the local clock events for a CPU.
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*/
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void __cpuinit local_timer_setup(unsigned int cpu)
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{
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struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
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unsigned long flags;
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/*
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* gettimeoffset() will return a number of us since the last tick.
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* Convert this number of us to a local timer tick count.
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* Be careful of integer overflow whilst keeping maximum precision.
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*
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* with HZ=100 and 1MHz (fpga) ~ 1GHz processor:
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* load = 1 ~ 10,000
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* mpcore_timer_rate/10000 = 100 ~ 100,000
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*
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* so the multiply value will be less than 10^9 always.
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*/
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load = (system_timer->offset() * (mpcore_timer_rate / 10000)) / 100;
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twd_calibrate_rate(cpu);
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/* Add on our offset to get the load value */
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load = (load + offset) % (mpcore_timer_rate / HZ);
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__raw_writel(load, base + TWD_TIMER_COUNTER);
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clk->name = "local_timer";
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clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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clk->rating = 350;
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clk->set_mode = local_timer_set_mode;
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clk->set_next_event = local_timer_set_next_event;
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clk->irq = IRQ_LOCALTIMER;
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clk->cpumask = cpumask_of_cpu(cpu);
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clk->shift = 20;
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clk->mult = div_sc(mpcore_timer_rate, NSEC_PER_SEC, clk->shift);
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clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
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clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
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/* Make sure our local interrupt controller has this enabled */
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__raw_writel(1 << IRQ_LOCALTIMER,
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__io_address(REALVIEW_GIC_DIST_BASE) + GIC_DIST_ENABLE_SET);
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local_irq_save(flags);
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get_irq_chip(IRQ_LOCALTIMER)->unmask(IRQ_LOCALTIMER);
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local_irq_restore(flags);
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clockevents_register_device(clk);
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}
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/*
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@ -1,7 +1,7 @@
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#ifndef __ASM_HARDWARE_TWD_H
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#define __ASM_HARDWARE_TWD_H
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#define TWD_TIMER_LOAD 0x00
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#define TWD_TIMER_LOAD 0x00
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#define TWD_TIMER_COUNTER 0x04
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#define TWD_TIMER_CONTROL 0x08
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#define TWD_TIMER_INTSTAT 0x0C
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@ -13,4 +13,9 @@
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#define TWD_WDOG_RESETSTAT 0x30
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#define TWD_WDOG_DISABLE 0x34
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#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
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#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
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#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
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#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
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#endif
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