MIPS: Octeon: Add support for accessing the boot vector.
Used by the Octeon watchdog driver to get the address of the firmware boot vector. Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17206/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
Steven J. Hill
Ralf Baechle
parent
d9a46c183a
commit
9438a86a07
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@ -16,4 +16,4 @@ obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
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cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
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cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
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obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o
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obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o cvmx-boot-vector.o
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@ -0,0 +1,167 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2017 Cavium, Inc.
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*/
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/*
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We install this program at the bootvector:
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------------------------------------
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.set noreorder
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.set nomacro
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.set noat
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reset_vector:
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dmtc0 $k0, $31, 0 # Save $k0 to DESAVE
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dmtc0 $k1, $31, 3 # Save $k1 to KScratch2
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mfc0 $k0, $12, 0 # Status
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mfc0 $k1, $15, 1 # Ebase
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ori $k0, 0x84 # Enable 64-bit addressing, set
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# ERL (should already be set)
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andi $k1, 0x3ff # mask out core ID
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mtc0 $k0, $12, 0 # Status
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sll $k1, 5
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lui $k0, 0xbfc0
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cache 17, 0($0) # Core-14345, clear L1 Dcache virtual
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# tags if the core hit an NMI
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ld $k0, 0x78($k0) # k0 <- (bfc00078) pointer to the reset vector
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synci 0($0) # Invalidate ICache to get coherent
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# view of target code.
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daddu $k0, $k0, $k1
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nop
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ld $k0, 0($k0) # k0 <- core specific target address
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dmfc0 $k1, $31, 3 # Restore $k1 from KScratch2
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beqz $k0, wait_loop # Spin in wait loop
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nop
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jr $k0
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nop
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nop # NOPs needed here to fill delay slots
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nop # on endian reversal of previous instructions
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wait_loop:
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wait
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nop
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b wait_loop
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nop
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nop
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nop
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------------------------------------
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0000000000000000 <reset_vector>:
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0: 40baf800 dmtc0 k0,c0_desave
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4: 40bbf803 dmtc0 k1,c0_kscratch2
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8: 401a6000 mfc0 k0,c0_status
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c: 401b7801 mfc0 k1,c0_ebase
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10: 375a0084 ori k0,k0,0x84
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14: 337b03ff andi k1,k1,0x3ff
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18: 409a6000 mtc0 k0,c0_status
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1c: 001bd940 sll k1,k1,0x5
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20: 3c1abfc0 lui k0,0xbfc0
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24: bc110000 cache 0x11,0(zero)
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28: df5a0078 ld k0,120(k0)
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2c: 041f0000 synci 0(zero)
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30: 035bd02d daddu k0,k0,k1
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34: 00000000 nop
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38: df5a0000 ld k0,0(k0)
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3c: 403bf803 dmfc0 k1,c0_kscratch2
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40: 13400005 beqz k0,58 <wait_loop>
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44: 00000000 nop
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48: 03400008 jr k0
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4c: 00000000 nop
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50: 00000000 nop
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54: 00000000 nop
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0000000000000058 <wait_loop>:
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58: 42000020 wait
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5c: 00000000 nop
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60: 1000fffd b 58 <wait_loop>
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64: 00000000 nop
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68: 00000000 nop
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6c: 00000000 nop
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*/
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#include <asm/octeon/cvmx-boot-vector.h>
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static unsigned long long _cvmx_bootvector_data[16] = {
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0x40baf80040bbf803ull, /* patch low order 8-bits if no KScratch*/
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0x401a6000401b7801ull,
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0x375a0084337b03ffull,
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0x409a6000001bd940ull,
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0x3c1abfc0bc110000ull,
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0xdf5a0078041f0000ull,
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0x035bd02d00000000ull,
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0xdf5a0000403bf803ull, /* patch low order 8-bits if no KScratch*/
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0x1340000500000000ull,
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0x0340000800000000ull,
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0x0000000000000000ull,
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0x4200002000000000ull,
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0x1000fffd00000000ull,
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0x0000000000000000ull,
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OCTEON_BOOT_MOVEABLE_MAGIC1,
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0 /* To be filled in with address of vector block*/
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};
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/* 2^10 CPUs */
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#define VECTOR_TABLE_SIZE (1024 * sizeof(struct cvmx_boot_vector_element))
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static void cvmx_boot_vector_init(void *mem)
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{
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uint64_t kseg0_mem;
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int i;
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memset(mem, 0, VECTOR_TABLE_SIZE);
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kseg0_mem = cvmx_ptr_to_phys(mem) | 0x8000000000000000ull;
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for (i = 0; i < 15; i++) {
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uint64_t v = _cvmx_bootvector_data[i];
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if (OCTEON_IS_OCTEON1PLUS() && (i == 0 || i == 7))
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v &= 0xffffffff00000000ull; /* KScratch not availble. */
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, v);
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}
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, 15 * 8);
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, kseg0_mem);
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
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}
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/**
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* Get a pointer to the per-core table of reset vector pointers
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*
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*/
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struct cvmx_boot_vector_element *cvmx_boot_vector_get(void)
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{
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struct cvmx_boot_vector_element *ret;
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ret = cvmx_bootmem_alloc_named_range_once(VECTOR_TABLE_SIZE, 0,
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(1ull << 32) - 1, 8, "__boot_vector1__", cvmx_boot_vector_init);
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return ret;
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}
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EXPORT_SYMBOL(cvmx_boot_vector_get);
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@ -44,6 +44,55 @@ static struct cvmx_bootmem_desc *cvmx_bootmem_desc;
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/* See header file for descriptions of functions */
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/**
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* This macro returns the size of a member of a structure.
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* Logically it is the same as "sizeof(s::field)" in C++, but
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* C lacks the "::" operator.
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*/
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#define SIZEOF_FIELD(s, field) sizeof(((s *)NULL)->field)
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/**
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* This macro returns a member of the
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* cvmx_bootmem_named_block_desc_t structure. These members can't
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* be directly addressed as they might be in memory not directly
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* reachable. In the case where bootmem is compiled with
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* LINUX_HOST, the structure itself might be located on a remote
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* Octeon. The argument "field" is the member name of the
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* cvmx_bootmem_named_block_desc_t to read. Regardless of the type
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* of the field, the return type is always a uint64_t. The "addr"
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* parameter is the physical address of the structure.
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*/
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#define CVMX_BOOTMEM_NAMED_GET_FIELD(addr, field) \
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__cvmx_bootmem_desc_get(addr, \
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offsetof(struct cvmx_bootmem_named_block_desc, field), \
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SIZEOF_FIELD(struct cvmx_bootmem_named_block_desc, field))
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/**
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* This function is the implementation of the get macros defined
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* for individual structure members. The argument are generated
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* by the macros inorder to read only the needed memory.
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*
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* @param base 64bit physical address of the complete structure
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* @param offset Offset from the beginning of the structure to the member being
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* accessed.
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* @param size Size of the structure member.
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*
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* @return Value of the structure member promoted into a uint64_t.
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*/
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static inline uint64_t __cvmx_bootmem_desc_get(uint64_t base, int offset,
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int size)
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{
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base = (1ull << 63) | (base + offset);
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switch (size) {
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case 4:
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return cvmx_read64_uint32(base);
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case 8:
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return cvmx_read64_uint64(base);
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default:
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return 0;
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}
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}
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/*
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* Wrapper functions are provided for reading/writing the size and
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* next block values as these may not be directly addressible (in 32
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@ -98,6 +147,42 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
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return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
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}
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void *cvmx_bootmem_alloc_named_range_once(uint64_t size, uint64_t min_addr,
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uint64_t max_addr, uint64_t align,
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char *name,
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void (*init) (void *))
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{
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int64_t addr;
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void *ptr;
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uint64_t named_block_desc_addr;
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named_block_desc_addr = (uint64_t)
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cvmx_bootmem_phy_named_block_find(name,
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(uint32_t)CVMX_BOOTMEM_FLAG_NO_LOCKING);
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if (named_block_desc_addr) {
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addr = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_desc_addr,
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base_addr);
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return cvmx_phys_to_ptr(addr);
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}
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addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr,
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align, name,
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(uint32_t)CVMX_BOOTMEM_FLAG_NO_LOCKING);
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if (addr < 0)
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return NULL;
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ptr = cvmx_phys_to_ptr(addr);
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if (init)
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init(ptr);
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else
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memset(ptr, 0, size);
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return ptr;
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}
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EXPORT_SYMBOL(cvmx_bootmem_alloc_named_range_once);
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void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
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uint64_t max_addr, uint64_t align,
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char *name)
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@ -0,0 +1,53 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003-2017 Cavium, Inc.
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*/
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#ifndef __CVMX_BOOT_VECTOR_H__
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#define __CVMX_BOOT_VECTOR_H__
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#include <asm/octeon/octeon.h>
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/*
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* The boot vector table is made up of an array of 1024 elements of
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* struct cvmx_boot_vector_element. There is one entry for each
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* possible MIPS CPUNum, indexed by the CPUNum.
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*
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* Once cvmx_boot_vector_get() returns a non-NULL value (indicating
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* success), NMI to a core will cause execution to transfer to the
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* target_ptr location for that core's entry in the vector table.
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*
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* The struct cvmx_boot_vector_element fields app0, app1, and app2 can
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* be used by the application that has set the target_ptr in any
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* application specific manner, they are not touched by the vectoring
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* code.
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*
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* The boot vector code clobbers the CP0_DESAVE register, and on
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* OCTEON II and later CPUs also clobbers CP0_KScratch2. All GP
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* registers are preserved, except on pre-OCTEON II CPUs, where k1 is
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* clobbered.
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*
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*/
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/*
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* Applications install the boot bus code in cvmx-boot-vector.c, which
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* uses this magic:
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*/
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#define OCTEON_BOOT_MOVEABLE_MAGIC1 0xdb00110ad358eacdull
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struct cvmx_boot_vector_element {
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/* kseg0 or xkphys address of target code. */
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uint64_t target_ptr;
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/* Three application specific arguments. */
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uint64_t app0;
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uint64_t app1;
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uint64_t app2;
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};
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struct cvmx_boot_vector_element *cvmx_boot_vector_get(void);
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#endif /* __CVMX_BOOT_VECTOR_H__ */
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@ -255,6 +255,34 @@ extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
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uint64_t max_addr, uint64_t align,
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char *name);
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/**
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* Allocate if needed a block of memory from a specific range of the
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* free list that was passed to the application by the bootloader, and
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* assign it a name in the global named block table. (part of the
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* cvmx_bootmem_descriptor_t structure) Named blocks can later be
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* freed. If the requested name block is already allocated, return
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* the pointer to block of memory. If request cannot be satisfied
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* within the address range specified, NULL is returned
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*
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* @param size Size in bytes of block to allocate
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* @param min_addr minimum address of range
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* @param max_addr maximum address of range
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* @param align Alignment of memory to be allocated. (must be a power of 2)
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* @param name name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
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* @param init Initialization function
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*
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* The initialization function is optional, if omitted the named block
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* is initialized to all zeros when it is created, i.e. once.
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*
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* @return pointer to block of memory, NULL on error
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*/
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void *cvmx_bootmem_alloc_named_range_once(uint64_t size,
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uint64_t min_addr,
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uint64_t max_addr,
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uint64_t align,
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char *name,
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void (*init) (void *));
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extern int cvmx_bootmem_free_named(char *name);
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/**
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Reference in New Issue