KVM: arm/arm64: vgic: Add distributor and redistributor access
VGICv3 Distributor and Redistributor registers are accessed using KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls. These registers are accessed as 32-bit and cpu mpidr value passed along with register offset is used to identify the cpu for redistributor registers access. The version of VGIC v3 specification is defined here Documentation/virtual/kvm/devices/arm-vgic-v3.txt Also update arch/arm/include/uapi/asm/kvm.h to compile for AArch32 mode. Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>hifive-unleashed-5.1
Vijaya Kumar K
Marc Zyngier
parent
2df903a89a
commit
94574c9488
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@ -181,10 +181,14 @@ struct kvm_arch_memory_slot {
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#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
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#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
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#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
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#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
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#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
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(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
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#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
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#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
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#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
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#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
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#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
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#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
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/* KVM_IRQ_LINE irq field index values */
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@ -201,10 +201,14 @@ struct kvm_arch_memory_slot {
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#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
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#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
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#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
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#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
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#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
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(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
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#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
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#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
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#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
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#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
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#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
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#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
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/* Device Control API on vcpu fd */
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@ -17,6 +17,7 @@
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#include <kvm/arm_vgic.h>
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#include <linux/uaccess.h>
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#include <asm/kvm_mmu.h>
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#include <asm/cputype.h>
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#include "vgic.h"
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/* common helpers */
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@ -230,14 +231,8 @@ int kvm_register_vgic_device(unsigned long type)
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return ret;
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}
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struct vgic_reg_attr {
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struct kvm_vcpu *vcpu;
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gpa_t addr;
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};
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static int parse_vgic_v2_attr(struct kvm_device *dev,
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struct kvm_device_attr *attr,
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struct vgic_reg_attr *reg_attr)
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int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
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struct vgic_reg_attr *reg_attr)
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{
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int cpuid;
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@ -292,14 +287,14 @@ static bool lock_all_vcpus(struct kvm *kvm)
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}
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/**
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* vgic_attr_regs_access_v2 - allows user space to access VGIC v2 state
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* vgic_v2_attr_regs_access - allows user space to access VGIC v2 state
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*
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* @dev: kvm device handle
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* @attr: kvm device attribute
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* @reg: address the value is read or written
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* @is_write: true if userspace is writing a register
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*/
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static int vgic_attr_regs_access_v2(struct kvm_device *dev,
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static int vgic_v2_attr_regs_access(struct kvm_device *dev,
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struct kvm_device_attr *attr,
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u32 *reg, bool is_write)
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{
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@ -308,7 +303,7 @@ static int vgic_attr_regs_access_v2(struct kvm_device *dev,
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struct kvm_vcpu *vcpu;
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int ret;
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ret = parse_vgic_v2_attr(dev, attr, ®_attr);
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ret = vgic_v2_parse_attr(dev, attr, ®_attr);
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if (ret)
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return ret;
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@ -362,7 +357,7 @@ static int vgic_v2_set_attr(struct kvm_device *dev,
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if (get_user(reg, uaddr))
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return -EFAULT;
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return vgic_attr_regs_access_v2(dev, attr, ®, true);
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return vgic_v2_attr_regs_access(dev, attr, ®, true);
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}
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}
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@ -384,7 +379,7 @@ static int vgic_v2_get_attr(struct kvm_device *dev,
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u32 __user *uaddr = (u32 __user *)(long)attr->addr;
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u32 reg = 0;
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ret = vgic_attr_regs_access_v2(dev, attr, ®, false);
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ret = vgic_v2_attr_regs_access(dev, attr, ®, false);
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if (ret)
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return ret;
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return put_user(reg, uaddr);
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@ -428,16 +423,149 @@ struct kvm_device_ops kvm_arm_vgic_v2_ops = {
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.has_attr = vgic_v2_has_attr,
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};
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int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
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struct vgic_reg_attr *reg_attr)
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{
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unsigned long vgic_mpidr, mpidr_reg;
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/*
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* For KVM_DEV_ARM_VGIC_GRP_DIST_REGS group,
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* attr might not hold MPIDR. Hence assume vcpu0.
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*/
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if (attr->group != KVM_DEV_ARM_VGIC_GRP_DIST_REGS) {
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vgic_mpidr = (attr->attr & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) >>
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KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT;
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mpidr_reg = VGIC_TO_MPIDR(vgic_mpidr);
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reg_attr->vcpu = kvm_mpidr_to_vcpu(dev->kvm, mpidr_reg);
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} else {
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reg_attr->vcpu = kvm_get_vcpu(dev->kvm, 0);
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}
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if (!reg_attr->vcpu)
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return -EINVAL;
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reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
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return 0;
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}
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/*
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* vgic_v3_attr_regs_access - allows user space to access VGIC v3 state
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*
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* @dev: kvm device handle
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* @attr: kvm device attribute
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* @reg: address the value is read or written
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* @is_write: true if userspace is writing a register
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*/
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static int vgic_v3_attr_regs_access(struct kvm_device *dev,
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struct kvm_device_attr *attr,
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u64 *reg, bool is_write)
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{
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struct vgic_reg_attr reg_attr;
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gpa_t addr;
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struct kvm_vcpu *vcpu;
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int ret;
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u32 tmp32;
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ret = vgic_v3_parse_attr(dev, attr, ®_attr);
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if (ret)
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return ret;
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vcpu = reg_attr.vcpu;
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addr = reg_attr.addr;
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mutex_lock(&dev->kvm->lock);
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if (unlikely(!vgic_initialized(dev->kvm))) {
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ret = -EBUSY;
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goto out;
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}
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if (!lock_all_vcpus(dev->kvm)) {
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ret = -EBUSY;
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goto out;
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}
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switch (attr->group) {
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case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
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if (is_write)
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tmp32 = *reg;
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ret = vgic_v3_dist_uaccess(vcpu, is_write, addr, &tmp32);
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if (!is_write)
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*reg = tmp32;
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break;
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case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
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if (is_write)
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tmp32 = *reg;
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ret = vgic_v3_redist_uaccess(vcpu, is_write, addr, &tmp32);
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if (!is_write)
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*reg = tmp32;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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unlock_all_vcpus(dev->kvm);
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out:
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mutex_unlock(&dev->kvm->lock);
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return ret;
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}
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static int vgic_v3_set_attr(struct kvm_device *dev,
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struct kvm_device_attr *attr)
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{
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return vgic_set_common_attr(dev, attr);
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int ret;
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ret = vgic_set_common_attr(dev, attr);
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if (ret != -ENXIO)
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return ret;
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switch (attr->group) {
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case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
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case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
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u32 __user *uaddr = (u32 __user *)(long)attr->addr;
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u32 tmp32;
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u64 reg;
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if (get_user(tmp32, uaddr))
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return -EFAULT;
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reg = tmp32;
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return vgic_v3_attr_regs_access(dev, attr, ®, true);
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}
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}
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return -ENXIO;
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}
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static int vgic_v3_get_attr(struct kvm_device *dev,
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struct kvm_device_attr *attr)
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{
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return vgic_get_common_attr(dev, attr);
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int ret;
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ret = vgic_get_common_attr(dev, attr);
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if (ret != -ENXIO)
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return ret;
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switch (attr->group) {
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case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
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case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: {
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u32 __user *uaddr = (u32 __user *)(long)attr->addr;
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u64 reg;
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u32 tmp32;
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ret = vgic_v3_attr_regs_access(dev, attr, ®, false);
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if (ret)
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return ret;
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tmp32 = reg;
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return put_user(tmp32, uaddr);
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}
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}
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return -ENXIO;
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}
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static int vgic_v3_has_attr(struct kvm_device *dev,
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@ -451,6 +579,9 @@ static int vgic_v3_has_attr(struct kvm_device *dev,
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return 0;
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}
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break;
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case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
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case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:
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return vgic_v3_has_attr_regs(dev, attr);
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case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
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return 0;
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case KVM_DEV_ARM_VGIC_GRP_CTRL:
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@ -369,21 +369,30 @@ unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
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int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
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{
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int nr_irqs = dev->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
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const struct vgic_register_region *regions;
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const struct vgic_register_region *region;
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struct vgic_io_device iodev;
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struct vgic_reg_attr reg_attr;
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struct kvm_vcpu *vcpu;
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gpa_t addr;
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int nr_regions, i, len;
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int ret;
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addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
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ret = vgic_v2_parse_attr(dev, attr, ®_attr);
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if (ret)
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return ret;
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vcpu = reg_attr.vcpu;
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addr = reg_attr.addr;
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switch (attr->group) {
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case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
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regions = vgic_v2_dist_registers;
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nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
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iodev.regions = vgic_v2_dist_registers;
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iodev.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
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iodev.base_addr = 0;
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break;
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case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
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regions = vgic_v2_cpu_registers;
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nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
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iodev.regions = vgic_v2_cpu_registers;
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iodev.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
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iodev.base_addr = 0;
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break;
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default:
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return -ENXIO;
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@ -393,18 +402,11 @@ int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
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if (addr & 3)
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return -ENXIO;
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for (i = 0; i < nr_regions; i++) {
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if (regions[i].bits_per_irq)
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len = (regions[i].bits_per_irq * nr_irqs) / 8;
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else
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len = regions[i].len;
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region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
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if (!region)
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return -ENXIO;
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if (regions[i].reg_offset <= addr &&
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regions[i].reg_offset + len > addr)
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return 0;
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}
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return -ENXIO;
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return 0;
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}
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int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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@ -18,6 +18,8 @@
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#include <kvm/arm_vgic.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmu.h>
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#include "vgic.h"
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#include "vgic-mmio.h"
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@ -433,6 +435,9 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
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vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
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vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
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vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1,
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VGIC_ACCESS_32bit),
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@ -480,12 +485,18 @@ static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
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vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
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vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
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vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
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vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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@ -606,6 +617,48 @@ int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
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return ret;
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}
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int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
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{
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const struct vgic_register_region *region;
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struct vgic_io_device iodev;
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struct vgic_reg_attr reg_attr;
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struct kvm_vcpu *vcpu;
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gpa_t addr;
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int ret;
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ret = vgic_v3_parse_attr(dev, attr, ®_attr);
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if (ret)
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return ret;
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vcpu = reg_attr.vcpu;
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addr = reg_attr.addr;
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switch (attr->group) {
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case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
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iodev.regions = vgic_v3_dist_registers;
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iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
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iodev.base_addr = 0;
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break;
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case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
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iodev.regions = vgic_v3_rdbase_registers;
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iodev.nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
|
||||
iodev.base_addr = 0;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
/* We only support aligned 32-bit accesses. */
|
||||
if (addr & 3)
|
||||
return -ENXIO;
|
||||
|
||||
region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
|
||||
if (!region)
|
||||
return -ENXIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*
|
||||
* Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
|
||||
* generation register ICC_SGI1R_EL1) with a given VCPU.
|
||||
|
|
@ -712,3 +765,35 @@ void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
|
|||
vgic_put_irq(vcpu->kvm, irq);
|
||||
}
|
||||
}
|
||||
|
||||
int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
|
||||
int offset, u32 *val)
|
||||
{
|
||||
struct vgic_io_device dev = {
|
||||
.regions = vgic_v3_dist_registers,
|
||||
.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
|
||||
};
|
||||
|
||||
return vgic_uaccess(vcpu, &dev, is_write, offset, val);
|
||||
}
|
||||
|
||||
int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
|
||||
int offset, u32 *val)
|
||||
{
|
||||
struct vgic_io_device rd_dev = {
|
||||
.regions = vgic_v3_rdbase_registers,
|
||||
.nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers),
|
||||
};
|
||||
|
||||
struct vgic_io_device sgi_dev = {
|
||||
.regions = vgic_v3_sgibase_registers,
|
||||
.nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers),
|
||||
};
|
||||
|
||||
/* SGI_base is the next 64K frame after RD_base */
|
||||
if (offset >= SZ_64K)
|
||||
return vgic_uaccess(vcpu, &sgi_dev, is_write, offset - SZ_64K,
|
||||
val);
|
||||
else
|
||||
return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -475,7 +475,7 @@ static bool check_region(const struct kvm *kvm,
|
|||
return false;
|
||||
}
|
||||
|
||||
static const struct vgic_register_region *
|
||||
const struct vgic_register_region *
|
||||
vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
|
||||
gpa_t addr, int len)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -30,6 +30,28 @@
|
|||
|
||||
#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
|
||||
|
||||
#define VGIC_AFFINITY_0_SHIFT 0
|
||||
#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
|
||||
#define VGIC_AFFINITY_1_SHIFT 8
|
||||
#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
|
||||
#define VGIC_AFFINITY_2_SHIFT 16
|
||||
#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
|
||||
#define VGIC_AFFINITY_3_SHIFT 24
|
||||
#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
|
||||
|
||||
#define VGIC_AFFINITY_LEVEL(reg, level) \
|
||||
((((reg) & VGIC_AFFINITY_## level ##_MASK) \
|
||||
>> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
|
||||
|
||||
/*
|
||||
* The Userspace encodes the affinity differently from the MPIDR,
|
||||
* Below macro converts vgic userspace format to MPIDR reg format.
|
||||
*/
|
||||
#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
|
||||
VGIC_AFFINITY_LEVEL(val, 1) | \
|
||||
VGIC_AFFINITY_LEVEL(val, 2) | \
|
||||
VGIC_AFFINITY_LEVEL(val, 3))
|
||||
|
||||
static inline bool irq_is_pending(struct vgic_irq *irq)
|
||||
{
|
||||
if (irq->config == VGIC_CONFIG_EDGE)
|
||||
|
|
@ -45,6 +67,18 @@ struct vgic_vmcr {
|
|||
u32 pmr;
|
||||
};
|
||||
|
||||
struct vgic_reg_attr {
|
||||
struct kvm_vcpu *vcpu;
|
||||
gpa_t addr;
|
||||
};
|
||||
|
||||
int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
|
||||
struct vgic_reg_attr *reg_attr);
|
||||
int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
|
||||
struct vgic_reg_attr *reg_attr);
|
||||
const struct vgic_register_region *
|
||||
vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
|
||||
gpa_t addr, int len);
|
||||
struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
|
||||
u32 intid);
|
||||
void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
|
||||
|
|
@ -97,7 +131,11 @@ bool vgic_has_its(struct kvm *kvm);
|
|||
int kvm_vgic_register_its_device(void);
|
||||
void vgic_enable_lpis(struct kvm_vcpu *vcpu);
|
||||
int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
|
||||
|
||||
int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
|
||||
int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
|
||||
int offset, u32 *val);
|
||||
int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
|
||||
int offset, u32 *val);
|
||||
int kvm_register_vgic_device(unsigned long type);
|
||||
int vgic_lazy_init(struct kvm *kvm);
|
||||
int vgic_init(struct kvm *kvm);
|
||||
|
|
|
|||
Loading…
Reference in New Issue