dmaengine: qcom_hidma: bring out interrupt cause
Bring out the interrupt cause to the top level so that MSI interrupts can be hooked at a later stage. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>hifive-unleashed-5.1
parent
bdcfddfd74
commit
9483d9ae09
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@ -418,12 +418,24 @@ static int hidma_ll_reset(struct hidma_lldev *lldev)
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* requests traditionally to the destination, this concept does not apply
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* requests traditionally to the destination, this concept does not apply
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* here for this HW.
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* here for this HW.
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*/
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*/
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irqreturn_t hidma_ll_inthandler(int chirq, void *arg)
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static void hidma_ll_int_handler_internal(struct hidma_lldev *lldev, int cause)
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{
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{
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struct hidma_lldev *lldev = arg;
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if (cause & HIDMA_ERR_INT_MASK) {
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u32 status;
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dev_err(lldev->dev, "error 0x%x, disabling...\n",
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u32 enable;
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cause);
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u32 cause;
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/* Clear out pending interrupts */
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writel(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
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/* No further submissions. */
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hidma_ll_disable(lldev);
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/* Driver completes the txn and intimates the client.*/
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hidma_cleanup_pending_tre(lldev, 0xFF,
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HIDMA_EVRE_STATUS_ERROR);
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return;
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}
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/*
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/*
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* Fine tuned for this HW...
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* Fine tuned for this HW...
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@ -432,35 +444,28 @@ irqreturn_t hidma_ll_inthandler(int chirq, void *arg)
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* read and write accessors are used for performance reasons due to
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* read and write accessors are used for performance reasons due to
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* interrupt delivery guarantees. Do not copy this code blindly and
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* interrupt delivery guarantees. Do not copy this code blindly and
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* expect that to work.
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* expect that to work.
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*
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* Try to consume as many EVREs as possible.
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*/
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*/
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hidma_handle_tre_completion(lldev);
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/* We consumed TREs or there are pending TREs or EVREs. */
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writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
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}
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irqreturn_t hidma_ll_inthandler(int chirq, void *arg)
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{
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struct hidma_lldev *lldev = arg;
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u32 status;
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u32 enable;
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u32 cause;
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status = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
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status = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
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enable = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
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enable = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
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cause = status & enable;
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cause = status & enable;
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while (cause) {
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while (cause) {
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if (cause & HIDMA_ERR_INT_MASK) {
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hidma_ll_int_handler_internal(lldev, cause);
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dev_err(lldev->dev, "error 0x%x, disabling...\n",
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cause);
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/* Clear out pending interrupts */
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writel(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
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/* No further submissions. */
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hidma_ll_disable(lldev);
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/* Driver completes the txn and intimates the client.*/
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hidma_cleanup_pending_tre(lldev, 0xFF,
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HIDMA_EVRE_STATUS_ERROR);
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goto out;
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}
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/*
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* Try to consume as many EVREs as possible.
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*/
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hidma_handle_tre_completion(lldev);
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/* We consumed TREs or there are pending TREs or EVREs. */
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writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
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/*
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/*
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* Another interrupt might have arrived while we are
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* Another interrupt might have arrived while we are
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@ -471,7 +476,6 @@ irqreturn_t hidma_ll_inthandler(int chirq, void *arg)
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cause = status & enable;
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cause = status & enable;
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}
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}
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out:
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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