Topic pull request for topic/phy-compliance:
- Standardize DP_PHY_TEST_PATTERN name. - Add support for setting/getting test pattern from sink. - Implement DP PHY compliance to i915. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuXvWqAysSYEJGuVH/lWMcqZwE8MFAl6Nx7IACgkQ/lWMcqZw E8NuUw//WdQYxyZPxmHni+qdc2815GnsIW3j1BjFBRwkGQi8lYS2quJqg1F9Bg6v Hfu5oQjySSw5OHydWfluuY+u4DvuX21HzqsJt6hRz6QcJD9k6VtAkDIHxSAEyUGm G9gQ0j6jo3lWoehquh00btNdCAbaa2vmCqsAyC7mI+tlZS6VZeBnVfgYjKT85JQl /8a04CE3JnCvVp77i2wRztWO+CQNP74yBstq4Exbu2CsfYmzpg2h1Ma7yY8XvauT BVQFX5kZURSBQNRZuuDw7M2xrrtaiHyDQRJVLv4/WcvFdSLmSMAerPagerXN3S/H hGJTv5LhKA0G5cdZlTqn0xeV1IDNl9N0pUsLvAC1IZmd7i0blg7106xrQRkMADJs I/kCv92YafzYkgyGYKQjii1oSiUYFe0jEirDyh9TJJnbxfS53vAn6v2iZLmLnxPk jgarrgDNfK8hpqXM73XPyt1VjO2p16/4OqE6HPMaTr9vEx2pp9u7hrXTdobkeQVB ZgQf/stF1okjvOaZ/aFsxrbXBpOzV3U0zh5oVdMLdDsNg30lvqoYEuw21gn/riF9 dEma7CSbUhgGO1/IAWEU9hxyqYxVO9mV0xDVzVT/GxLP52GMTb+0eGvmgUTsCa6X 0lhvn636GRn2gogoSp9AqxZtmS3ergqr3iTPcLb9O0xS4zyrsTQ= =ubxj -----END PGP SIGNATURE----- Merge tag 'topic/phy-compliance-2020-04-08' of git://anongit.freedesktop.org/drm/drm-misc into drm-misc-next Topic pull request for topic/phy-compliance: - Standardize DP_PHY_TEST_PATTERN name. - Add support for setting/getting test pattern from sink. - Implement DP PHY compliance to i915. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> # gpg: Signatur vom Mi 08 Apr 2020 14:46:42 CEST # gpg: mittels RSA-Schlüssel B97BD6A80CAC4981091AE547FE558C72A67013C3 # gpg: Signatur kann nicht geprüft werden: Kein öffentlicher Schlüssel From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/efb3d0d9-2cf7-046b-3a9b-2548d086258e@linux.intel.com
This commit is contained in:
commit
948565468c
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@ -2530,7 +2530,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link)
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/* get phy test pattern and pattern parameters from DP receiver */
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core_link_read_dpcd(
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link,
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DP_TEST_PHY_PATTERN,
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DP_PHY_TEST_PATTERN,
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&dpcd_test_pattern.raw,
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sizeof(dpcd_test_pattern));
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core_link_read_dpcd(
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@ -1533,3 +1533,97 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
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return num_bpc;
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}
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EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
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/**
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* drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
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* @aux: DisplayPort AUX channel
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* @data: DP phy compliance test parameters.
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*
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* Returns 0 on success or a negative error code on failure.
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*/
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int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
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struct drm_dp_phy_test_params *data)
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{
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int err;
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u8 rate, lanes;
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err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
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if (err < 0)
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return err;
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data->link_rate = drm_dp_bw_code_to_link_rate(rate);
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err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
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if (err < 0)
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return err;
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data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
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if (lanes & DP_ENHANCED_FRAME_CAP)
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data->enhanced_frame_cap = true;
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err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
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if (err < 0)
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return err;
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switch (data->phy_pattern) {
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case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
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err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
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&data->custom80, sizeof(data->custom80));
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if (err < 0)
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return err;
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break;
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case DP_PHY_TEST_PATTERN_CP2520:
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err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
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&data->hbr2_reset,
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sizeof(data->hbr2_reset));
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if (err < 0)
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return err;
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}
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return 0;
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}
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EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
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/**
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* drm_dp_set_phy_test_pattern() - set the pattern to the sink.
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* @aux: DisplayPort AUX channel
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* @data: DP phy compliance test parameters.
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*
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* Returns 0 on success or a negative error code on failure.
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*/
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int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
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struct drm_dp_phy_test_params *data, u8 dp_rev)
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{
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int err, i;
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u8 link_config[2];
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u8 test_pattern;
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link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
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link_config[1] = data->num_lanes;
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if (data->enhanced_frame_cap)
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link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
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if (err < 0)
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return err;
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test_pattern = data->phy_pattern;
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if (dp_rev < 0x12) {
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test_pattern = (test_pattern << 2) &
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DP_LINK_QUAL_PATTERN_11_MASK;
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err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
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test_pattern);
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if (err < 0)
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return err;
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} else {
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for (i = 0; i < data->num_lanes; i++) {
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err = drm_dp_dpcd_writeb(aux,
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DP_LINK_QUAL_LANE0_SET + i,
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test_pattern);
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if (err < 0)
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return err;
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}
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}
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return 0;
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}
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EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
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@ -1320,6 +1320,16 @@ static int i915_displayport_test_data_show(struct seq_file *m, void *data)
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intel_dp->compliance.test_data.vdisplay);
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seq_printf(m, "bpc: %u\n",
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intel_dp->compliance.test_data.bpc);
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} else if (intel_dp->compliance.test_type ==
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DP_TEST_LINK_PHY_TEST_PATTERN) {
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seq_printf(m, "pattern: %d\n",
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intel_dp->compliance.test_data.phytest.phy_pattern);
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seq_printf(m, "Number of lanes: %d\n",
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intel_dp->compliance.test_data.phytest.num_lanes);
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seq_printf(m, "Link Rate: %d\n",
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intel_dp->compliance.test_data.phytest.link_rate);
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seq_printf(m, "level: %02x\n",
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intel_dp->train_set[0]);
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}
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} else
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seq_puts(m, "0");
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@ -1352,7 +1362,7 @@ static int i915_displayport_test_type_show(struct seq_file *m, void *data)
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if (encoder && connector->status == connector_status_connected) {
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intel_dp = enc_to_intel_dp(encoder);
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seq_printf(m, "%02lx", intel_dp->compliance.test_type);
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seq_printf(m, "%02lx\n", intel_dp->compliance.test_type);
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} else
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seq_puts(m, "0");
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}
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@ -1238,6 +1238,7 @@ struct intel_dp_compliance_data {
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u8 video_pattern;
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u16 hdisplay, vdisplay;
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u8 bpc;
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struct drm_dp_phy_test_params phytest;
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};
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struct intel_dp_compliance {
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@ -5001,9 +5001,180 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
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return test_result;
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}
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static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
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{
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struct drm_dp_phy_test_params *data =
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&intel_dp->compliance.test_data.phytest;
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if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
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DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
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return DP_TEST_NAK;
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}
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/*
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* link_mst is set to false to avoid executing mst related code
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* during compliance testing.
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*/
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intel_dp->link_mst = false;
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return DP_TEST_ACK;
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}
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static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
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{
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struct drm_i915_private *dev_priv =
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to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_dp_phy_test_params *data =
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&intel_dp->compliance.test_data.phytest;
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struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
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enum pipe pipe = crtc->pipe;
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u32 pattern_val;
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switch (data->phy_pattern) {
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case DP_PHY_TEST_PATTERN_NONE:
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DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
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intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
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break;
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case DP_PHY_TEST_PATTERN_D10_2:
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DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
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intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
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DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
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break;
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case DP_PHY_TEST_PATTERN_ERROR_COUNT:
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DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
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intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
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DDI_DP_COMP_CTL_ENABLE |
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DDI_DP_COMP_CTL_SCRAMBLED_0);
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break;
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case DP_PHY_TEST_PATTERN_PRBS7:
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DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
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intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
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DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
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break;
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case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
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/*
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* FIXME: Ideally pattern should come from DPCD 0x250. As
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* current firmware of DPR-100 could not set it, so hardcoding
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* now for complaince test.
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*/
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DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
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pattern_val = 0x3e0f83e0;
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intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
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pattern_val = 0x0f83e0f8;
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intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
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pattern_val = 0x0000f83e;
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intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
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intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
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DDI_DP_COMP_CTL_ENABLE |
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DDI_DP_COMP_CTL_CUSTOM80);
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break;
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case DP_PHY_TEST_PATTERN_CP2520:
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/*
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* FIXME: Ideally pattern should come from DPCD 0x24A. As
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* current firmware of DPR-100 could not set it, so hardcoding
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* now for complaince test.
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*/
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DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
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pattern_val = 0xFB;
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intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
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DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
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pattern_val);
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break;
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default:
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WARN(1, "Invalid Phy Test Pattern\n");
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}
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}
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static void
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intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = intel_dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
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enum pipe pipe = crtc->pipe;
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u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
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trans_ddi_func_ctl_value = intel_de_read(dev_priv,
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TRANS_DDI_FUNC_CTL(pipe));
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trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
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dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
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trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
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TGL_TRANS_DDI_PORT_MASK);
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trans_conf_value &= ~PIPECONF_ENABLE;
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dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
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intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
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intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
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trans_ddi_func_ctl_value);
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intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
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}
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static void
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intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = intel_dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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enum port port = intel_dig_port->base.port;
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struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
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enum pipe pipe = crtc->pipe;
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u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
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trans_ddi_func_ctl_value = intel_de_read(dev_priv,
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TRANS_DDI_FUNC_CTL(pipe));
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trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
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dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
|
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|
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trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
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TGL_TRANS_DDI_SELECT_PORT(port);
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trans_conf_value |= PIPECONF_ENABLE;
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dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
|
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|
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intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
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intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
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intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
|
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trans_ddi_func_ctl_value);
|
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}
|
||||
|
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void intel_dp_process_phy_request(struct intel_dp *intel_dp)
|
||||
{
|
||||
struct drm_dp_phy_test_params *data =
|
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&intel_dp->compliance.test_data.phytest;
|
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u8 link_status[DP_LINK_STATUS_SIZE];
|
||||
|
||||
if (!intel_dp_get_link_status(intel_dp, link_status)) {
|
||||
DRM_DEBUG_KMS("failed to get link status\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* retrieve vswing & pre-emphasis setting */
|
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intel_dp_get_adjust_train(intel_dp, link_status);
|
||||
|
||||
intel_dp_autotest_phy_ddi_disable(intel_dp);
|
||||
|
||||
intel_dp_set_signal_levels(intel_dp);
|
||||
|
||||
intel_dp_phy_pattern_update(intel_dp);
|
||||
|
||||
intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
|
||||
|
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drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
|
||||
link_status[DP_DPCD_REV]);
|
||||
}
|
||||
|
||||
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
|
||||
{
|
||||
u8 test_result = DP_TEST_NAK;
|
||||
|
||||
test_result = intel_dp_prepare_phytest(intel_dp);
|
||||
if (test_result != DP_TEST_ACK)
|
||||
DRM_ERROR("Phy test preparation failed\n");
|
||||
|
||||
intel_dp_process_phy_request(intel_dp);
|
||||
|
||||
return test_result;
|
||||
}
|
||||
|
||||
|
|
|
@ -115,6 +115,7 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
|
|||
const struct intel_crtc_state *crtc_state,
|
||||
const struct drm_connector_state *conn_state);
|
||||
bool intel_digital_port_connected(struct intel_encoder *encoder);
|
||||
void intel_dp_process_phy_request(struct intel_dp *intel_dp);
|
||||
|
||||
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
|
||||
{
|
||||
|
|
|
@ -34,9 +34,8 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
|
|||
link_status[3], link_status[4], link_status[5]);
|
||||
}
|
||||
|
||||
static void
|
||||
intel_get_adjust_train(struct intel_dp *intel_dp,
|
||||
const u8 link_status[DP_LINK_STATUS_SIZE])
|
||||
void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
|
||||
const u8 link_status[DP_LINK_STATUS_SIZE])
|
||||
{
|
||||
u8 v = 0;
|
||||
u8 p = 0;
|
||||
|
@ -219,7 +218,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
|
|||
voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
|
||||
|
||||
/* Update training set as requested by target */
|
||||
intel_get_adjust_train(intel_dp, link_status);
|
||||
intel_dp_get_adjust_train(intel_dp, link_status);
|
||||
if (!intel_dp_update_link_train(intel_dp)) {
|
||||
drm_err(&i915->drm,
|
||||
"failed to update link training\n");
|
||||
|
@ -338,7 +337,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
|
|||
}
|
||||
|
||||
/* Update training set as requested by target */
|
||||
intel_get_adjust_train(intel_dp, link_status);
|
||||
intel_dp_get_adjust_train(intel_dp, link_status);
|
||||
if (!intel_dp_update_link_train(intel_dp)) {
|
||||
drm_err(&i915->drm,
|
||||
"failed to update link training\n");
|
||||
|
|
|
@ -6,8 +6,12 @@
|
|||
#ifndef __INTEL_DP_LINK_TRAINING_H__
|
||||
#define __INTEL_DP_LINK_TRAINING_H__
|
||||
|
||||
#include <drm/drm_dp_helper.h>
|
||||
|
||||
struct intel_dp;
|
||||
|
||||
void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
|
||||
const u8 link_status[DP_LINK_STATUS_SIZE]);
|
||||
void intel_dp_start_link_train(struct intel_dp *intel_dp);
|
||||
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
|
||||
|
||||
|
|
|
@ -9794,6 +9794,24 @@ enum skl_power_gate {
|
|||
#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
|
||||
#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
|
||||
|
||||
/* DDI DP Compliance Control */
|
||||
#define _DDI_DP_COMP_CTL_A 0x605F0
|
||||
#define _DDI_DP_COMP_CTL_B 0x615F0
|
||||
#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
|
||||
#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
|
||||
#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
|
||||
#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
|
||||
#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
|
||||
#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
|
||||
#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
|
||||
#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
|
||||
#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
|
||||
|
||||
/* DDI DP Compliance Pattern */
|
||||
#define _DDI_DP_COMP_PAT_A 0x605F4
|
||||
#define _DDI_DP_COMP_PAT_B 0x615F4
|
||||
#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
|
||||
|
||||
/* Sideband Interface (SBI) is programmed indirectly, via
|
||||
* SBI_ADDR, which contains the register offset; and SBI_DATA,
|
||||
* which contains the payload */
|
||||
|
|
|
@ -701,7 +701,16 @@
|
|||
# define DP_TEST_CRC_SUPPORTED (1 << 5)
|
||||
# define DP_TEST_COUNT_MASK 0xf
|
||||
|
||||
#define DP_TEST_PHY_PATTERN 0x248
|
||||
#define DP_PHY_TEST_PATTERN 0x248
|
||||
# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
|
||||
# define DP_PHY_TEST_PATTERN_NONE 0x0
|
||||
# define DP_PHY_TEST_PATTERN_D10_2 0x1
|
||||
# define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
|
||||
# define DP_PHY_TEST_PATTERN_PRBS7 0x3
|
||||
# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
|
||||
# define DP_PHY_TEST_PATTERN_CP2520 0x5
|
||||
|
||||
#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
|
||||
#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
|
||||
#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
|
||||
#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
|
||||
|
@ -1598,4 +1607,26 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
|
|||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* struct drm_dp_phy_test_params - DP Phy Compliance parameters
|
||||
* @link_rate: Requested Link rate from DPCD 0x219
|
||||
* @num_lanes: Number of lanes requested by sing through DPCD 0x220
|
||||
* @phy_pattern: DP Phy test pattern from DPCD 0x248
|
||||
* @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
|
||||
* @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
|
||||
* @enhanced_frame_cap: flag for enhanced frame capability.
|
||||
*/
|
||||
struct drm_dp_phy_test_params {
|
||||
int link_rate;
|
||||
u8 num_lanes;
|
||||
u8 phy_pattern;
|
||||
u8 hbr2_reset[2];
|
||||
u8 custom80[10];
|
||||
bool enhanced_frame_cap;
|
||||
};
|
||||
|
||||
int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
|
||||
struct drm_dp_phy_test_params *data);
|
||||
int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
|
||||
struct drm_dp_phy_test_params *data, u8 dp_rev);
|
||||
#endif /* _DRM_DP_HELPER_H_ */
|
||||
|
|
Loading…
Reference in a new issue