MIPS changes for 4.17
These are the main MIPS changes for 4.17. Rough overview:
(1) generic platform: Add support for Microsemi Ocelot SoCs
(2) crypto: Add CRC32 and CRC32C HW acceleration module
(3) Various cleanups and misc improvements
Miscellaneous:
- Hang more efficiently on halt/powerdown/restart
- pm-cps: Block system suspend when a JTAG probe is present
- Expand make help text for generic defconfigs
- Refactor handling of legacy defconfigs
- Determine the entry point from the ELF file header to fix microMIPS
for certain toolchains
- Introduce isa-rev.h for MIPS_ISA_REV and use to simplify other code
Minor cleanups:
- DTS: boston/ci20: Unit name cleanups and correction
- kdump: Make the default for PHYSICAL_START always 64-bit
- Constify gpio_led in Alchemy, AR7, and TXX9
- Silence a couple of W=1 warnings
- Remove duplicate includes
Platform support:
ath79:
- Fix AR724X_PLL_REG_PCIE_CONFIG offset
BCM47xx:
- FIRMWARE: Use mac_pton() for MAC address parsing
- Add Luxul XAP1500/XWR1750 WiFi LEDs
- Use standard reset button for Luxul XWR-1750
BMIPS:
- Enable CONFIG_BRCMSTB_PM in bmips_stb_defconfig for build coverage
- Add STB PM, wake-up timer, watchdog DT nodes
Generic platform:
- Add support for Microsemi Ocelot
- dt-bindings: Add vendor prefix for Microsemi Corporation
- dt-bindings: Add bindings for Microsemi SoCs
- Add ocelot SoC & PCB123 board DTS files
- MAINTAINERS: Add entry for Microsemi MIPS SoCs
- Enable crc32-mips on r6 configs
Octeon:
- Drop '.' after newlines in printk calls
ralink:
- pci-mt7621: Enable PCIe on MT7688
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Merge tag 'mips_4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips
Pull MIPS updates from James Hogan:
"These are the main MIPS changes for 4.17. Rough overview:
(1) generic platform: Add support for Microsemi Ocelot SoCs
(2) crypto: Add CRC32 and CRC32C HW acceleration module
(3) Various cleanups and misc improvements
More detailed summary:
Miscellaneous:
- hang more efficiently on halt/powerdown/restart
- pm-cps: Block system suspend when a JTAG probe is present
- expand make help text for generic defconfigs
- refactor handling of legacy defconfigs
- determine the entry point from the ELF file header to fix microMIPS
for certain toolchains
- introduce isa-rev.h for MIPS_ISA_REV and use to simplify other code
Minor cleanups:
- DTS: boston/ci20: Unit name cleanups and correction
- kdump: Make the default for PHYSICAL_START always 64-bit
- constify gpio_led in Alchemy, AR7, and TXX9
- silence a couple of W=1 warnings
- remove duplicate includes
Platform support:
Generic platform:
- add support for Microsemi Ocelot
- dt-bindings: Add vendor prefix for Microsemi Corporation
- dt-bindings: Add bindings for Microsemi SoCs
- add ocelot SoC & PCB123 board DTS files
- MAINTAINERS: Add entry for Microsemi MIPS SoCs
- enable crc32-mips on r6 configs
ath79:
- fix AR724X_PLL_REG_PCIE_CONFIG offset
BCM47xx:
- firmware: Use mac_pton() for MAC address parsing
- add Luxul XAP1500/XWR1750 WiFi LEDs
- use standard reset button for Luxul XWR-1750
BMIPS:
- enable CONFIG_BRCMSTB_PM in bmips_stb_defconfig for build coverage
- add STB PM, wake-up timer, watchdog DT nodes
Octeon:
- drop '.' after newlines in printk calls
ralink:
- pci-mt7621: Enable PCIe on MT7688"
* tag 'mips_4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (37 commits)
MIPS: BCM47XX: Use standard reset button for Luxul XWR-1750
MIPS: BCM47XX: Add Luxul XAP1500/XWR1750 WiFi LEDs
MIPS: Make the default for PHYSICAL_START always 64-bit
MIPS: Use the entry point from the ELF file header
MAINTAINERS: Add entry for Microsemi MIPS SoCs
MIPS: generic: Add support for Microsemi Ocelot
MIPS: mscc: Add ocelot PCB123 device tree
MIPS: mscc: Add ocelot dtsi
dt-bindings: mips: Add bindings for Microsemi SoCs
dt-bindings: Add vendor prefix for Microsemi Corporation
MIPS: ath79: Fix AR724X_PLL_REG_PCIE_CONFIG offset
MIPS: pci-mt7620: Enable PCIe on MT7688
MIPS: pm-cps: Block system suspend when a JTAG probe is present
MIPS: VDSO: Replace __mips_isa_rev with MIPS_ISA_REV
MIPS: BPF: Replace __mips_isa_rev with MIPS_ISA_REV
MIPS: cpu-features.h: Replace __mips_isa_rev with MIPS_ISA_REV
MIPS: Introduce isa-rev.h to define MIPS_ISA_REV
MIPS: Hang more efficiently on halt/powerdown/restart
FIRMWARE: bcm47xx_nvram: Replace mac address parsing
MIPS: BMIPS: Add Broadcom STB watchdog nodes
...
hifive-unleashed-5.1
Linus Torvalds
commit
948869fa9f
|
|
@ -0,0 +1,43 @@
|
|||
* Microsemi MIPS CPUs
|
||||
|
||||
Boards with a SoC of the Microsemi MIPS family shall have the following
|
||||
properties:
|
||||
|
||||
Required properties:
|
||||
- compatible: "mscc,ocelot"
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||||
|
||||
|
||||
* Other peripherals:
|
||||
|
||||
o CPU chip regs:
|
||||
|
||||
The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
|
||||
functionalities: chip ID, general purpose register for software use, reset
|
||||
controller, hardware status and configuration, efuses.
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||||
|
||||
Required properties:
|
||||
- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
|
||||
- reg : Should contain registers location and length
|
||||
|
||||
Example:
|
||||
syscon@71070000 {
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compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
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reg = <0x71070000 0x1c>;
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};
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o CPU system control:
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||||
|
||||
The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
|
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the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
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endianness, CPU bus control, CPU status.
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||||
|
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Required properties:
|
||||
- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
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- reg : Should contain registers location and length
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Example:
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syscon@70000000 {
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compatible = "mscc,ocelot-cpu-syscon", "syscon";
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reg = <0x70000000 0x2c>;
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};
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|
|
@ -225,6 +225,7 @@ motorola Motorola, Inc.
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|||
moxa Moxa Inc.
|
||||
mpl MPL AG
|
||||
mqmaker mqmaker Inc.
|
||||
mscc Microsemi Corporation
|
||||
msi Micro-Star International Co. Ltd.
|
||||
mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
|
||||
multi-inno Multi-Inno Technology Co.,Ltd
|
||||
|
|
|
|||
|
|
@ -9230,6 +9230,15 @@ S: Maintained
|
|||
F: drivers/usb/misc/usb251xb.c
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F: Documentation/devicetree/bindings/usb/usb251xb.txt
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MICROSEMI MIPS SOCS
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M: Alexandre Belloni <alexandre.belloni@bootlin.com>
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L: linux-mips@linux-mips.org
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S: Maintained
|
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F: arch/mips/generic/board-ocelot.c
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||||
F: arch/mips/configs/generic/board-ocelot.config
|
||||
F: arch/mips/boot/dts/mscc/
|
||||
F: Documentation/devicetree/bindings/mips/mscc.txt
|
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|
||||
MICROSEMI SMART ARRAY SMARTPQI DRIVER (smartpqi)
|
||||
M: Don Brace <don.brace@microsemi.com>
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L: esc.storagedev@microsemi.com
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|
|
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|||
|
|
@ -2029,6 +2029,7 @@ config CPU_MIPSR6
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select CPU_HAS_RIXI
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select HAVE_ARCH_BITREVERSE
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select MIPS_ASID_BITS_VARIABLE
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select MIPS_CRC_SUPPORT
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select MIPS_SPRAM
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config EVA
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|
@ -2502,6 +2503,9 @@ config MIPS_ASID_BITS
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|||
config MIPS_ASID_BITS_VARIABLE
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bool
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config MIPS_CRC_SUPPORT
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||||
bool
|
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|
||||
#
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||||
# - Highmem only makes sense for the 32-bit kernel.
|
||||
# - The current highmem code will only work properly on physically indexed
|
||||
|
|
@ -2850,8 +2854,7 @@ config CRASH_DUMP
|
|||
|
||||
config PHYSICAL_START
|
||||
hex "Physical address where the kernel is loaded"
|
||||
default "0xffffffff84000000" if 64BIT
|
||||
default "0x84000000" if 32BIT
|
||||
default "0xffffffff84000000"
|
||||
depends on CRASH_DUMP
|
||||
help
|
||||
This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
|
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|
|
|
|||
|
|
@ -222,6 +222,8 @@ xpa-cflags-y := $(mips-cflags)
|
|||
xpa-cflags-$(micromips-ase) += -mmicromips -Wa$(comma)-fatal-warnings
|
||||
toolchain-xpa := $(call cc-option-yn,$(xpa-cflags-y) -mxpa)
|
||||
cflags-$(toolchain-xpa) += -DTOOLCHAIN_SUPPORTS_XPA
|
||||
toolchain-crc := $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mcrc)
|
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cflags-$(toolchain-crc) += -DTOOLCHAIN_SUPPORTS_CRC
|
||||
|
||||
#
|
||||
# Firmware support
|
||||
|
|
@ -249,20 +251,12 @@ ifdef CONFIG_PHYSICAL_START
|
|||
load-y = $(CONFIG_PHYSICAL_START)
|
||||
endif
|
||||
|
||||
entry-noisa-y = 0x$(shell $(NM) vmlinux 2>/dev/null \
|
||||
| grep "\bkernel_entry\b" | cut -f1 -d \ )
|
||||
ifdef CONFIG_CPU_MICROMIPS
|
||||
#
|
||||
# Set the ISA bit, since the kernel_entry symbol in the ELF will have it
|
||||
# clear which would lead to images containing addresses which bootloaders may
|
||||
# jump to as MIPS32 code.
|
||||
#
|
||||
entry-y = $(patsubst %0,%1,$(patsubst %2,%3,$(patsubst %4,%5, \
|
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$(patsubst %6,%7,$(patsubst %8,%9,$(patsubst %a,%b, \
|
||||
$(patsubst %c,%d,$(patsubst %e,%f,$(entry-noisa-y)))))))))
|
||||
else
|
||||
entry-y = $(entry-noisa-y)
|
||||
endif
|
||||
# Sign-extend the entry point to 64 bits if retrieved as a 32-bit number.
|
||||
entry-y = $(shell $(OBJDUMP) -f vmlinux 2>/dev/null \
|
||||
| sed -n '/^start address / { \
|
||||
s/^.* //; \
|
||||
s/0x\([0-7].......\)$$/0x00000000\1/; \
|
||||
s/0x\(........\)$$/0xffffffff\1/; p }')
|
||||
|
||||
cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
|
||||
drivers-$(CONFIG_PCI) += arch/mips/pci/
|
||||
|
|
@ -330,6 +324,7 @@ libs-y += arch/mips/math-emu/
|
|||
# See arch/mips/Kbuild for content of core part of the kernel
|
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core-y += arch/mips/
|
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|
||||
drivers-$(CONFIG_MIPS_CRC_SUPPORT) += arch/mips/crypto/
|
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drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
|
||||
|
||||
# suspend and hibernation support
|
||||
|
|
@ -473,6 +468,21 @@ define archhelp
|
|||
echo
|
||||
echo ' {micro32,32,64}{r1,r2,r6}{el,}_defconfig <BOARDS="list of boards">'
|
||||
echo
|
||||
echo ' Where BOARDS is some subset of the following:'
|
||||
for board in $(sort $(BOARDS)); do echo " $${board}"; done
|
||||
echo
|
||||
echo ' Specifically the following generic default configurations are'
|
||||
echo ' supported:'
|
||||
echo
|
||||
$(foreach cfg,$(generic_defconfigs),
|
||||
printf " %-24s - Build generic kernel for $(call describe_generic_defconfig,$(cfg))\n" $(cfg);)
|
||||
echo
|
||||
echo ' The following legacy default configurations have been converted to'
|
||||
echo ' generic and can still be used:'
|
||||
echo
|
||||
$(foreach cfg,$(sort $(legacy_defconfigs)),
|
||||
printf " %-24s - Build $($(cfg)-y)\n" $(cfg);)
|
||||
echo
|
||||
echo ' Otherwise, the following default configurations are available:'
|
||||
endef
|
||||
|
||||
|
|
@ -507,6 +517,10 @@ endef
|
|||
$(eval $(call gen_generic_defconfigs,32 64,r1 r2 r6,eb el))
|
||||
$(eval $(call gen_generic_defconfigs,micro32,r2,eb el))
|
||||
|
||||
define describe_generic_defconfig
|
||||
$(subst 32r,MIPS32 r,$(subst 64r,MIPS64 r,$(subst el, little endian,$(patsubst %_defconfig,%,$(1)))))
|
||||
endef
|
||||
|
||||
.PHONY: $(generic_defconfigs)
|
||||
$(generic_defconfigs):
|
||||
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh \
|
||||
|
|
@ -543,14 +557,18 @@ generic_defconfig:
|
|||
# now that the boards have been converted to use the generic kernel they are
|
||||
# wrappers around the generic rules above.
|
||||
#
|
||||
.PHONY: sead3_defconfig
|
||||
sead3_defconfig:
|
||||
$(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=sead-3
|
||||
legacy_defconfigs += ocelot_defconfig
|
||||
ocelot_defconfig-y := 32r2el_defconfig BOARDS=ocelot
|
||||
|
||||
.PHONY: sead3micro_defconfig
|
||||
sead3micro_defconfig:
|
||||
$(Q)$(MAKE) -f $(srctree)/Makefile micro32r2el_defconfig BOARDS=sead-3
|
||||
legacy_defconfigs += sead3_defconfig
|
||||
sead3_defconfig-y := 32r2el_defconfig BOARDS=sead-3
|
||||
|
||||
.PHONY: xilfpga_defconfig
|
||||
xilfpga_defconfig:
|
||||
$(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=xilfpga
|
||||
legacy_defconfigs += sead3micro_defconfig
|
||||
sead3micro_defconfig-y := micro32r2el_defconfig BOARDS=sead-3
|
||||
|
||||
legacy_defconfigs += xilfpga_defconfig
|
||||
xilfpga_defconfig-y := 32r2el_defconfig BOARDS=xilfpga
|
||||
|
||||
.PHONY: $(legacy_defconfigs)
|
||||
$(legacy_defconfigs):
|
||||
$(Q)$(MAKE) -f $(srctree)/Makefile $($@-y)
|
||||
|
|
|
|||
|
|
@ -190,7 +190,7 @@ static struct platform_device gpr_mtd_device = {
|
|||
/*
|
||||
* LEDs
|
||||
*/
|
||||
static struct gpio_led gpr_gpio_leds[] = {
|
||||
static const struct gpio_led gpr_gpio_leds[] = {
|
||||
{ /* green */
|
||||
.name = "gpr:green",
|
||||
.gpio = 4,
|
||||
|
|
|
|||
|
|
@ -145,7 +145,7 @@ static struct platform_device mtx1_wdt = {
|
|||
.resource = mtx1_wdt_res,
|
||||
};
|
||||
|
||||
static struct gpio_led default_leds[] = {
|
||||
static const struct gpio_led default_leds[] = {
|
||||
{
|
||||
.name = "mtx1:green",
|
||||
.gpio = 211,
|
||||
|
|
|
|||
|
|
@ -346,7 +346,7 @@ static struct platform_device ar7_udc = {
|
|||
/*****************************************************************************
|
||||
* LEDs
|
||||
****************************************************************************/
|
||||
static struct gpio_led default_leds[] = {
|
||||
static const struct gpio_led default_leds[] = {
|
||||
{
|
||||
.name = "status",
|
||||
.gpio = 8,
|
||||
|
|
@ -354,12 +354,12 @@ static struct gpio_led default_leds[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct gpio_led titan_leds[] = {
|
||||
static const struct gpio_led titan_leds[] = {
|
||||
{ .name = "status", .gpio = 8, .active_low = 1, },
|
||||
{ .name = "wifi", .gpio = 13, .active_low = 1, },
|
||||
};
|
||||
|
||||
static struct gpio_led dsl502t_leds[] = {
|
||||
static const struct gpio_led dsl502t_leds[] = {
|
||||
{
|
||||
.name = "status",
|
||||
.gpio = 9,
|
||||
|
|
@ -377,7 +377,7 @@ static struct gpio_led dsl502t_leds[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct gpio_led dg834g_leds[] = {
|
||||
static const struct gpio_led dg834g_leds[] = {
|
||||
{
|
||||
.name = "ppp",
|
||||
.gpio = 6,
|
||||
|
|
@ -406,7 +406,7 @@ static struct gpio_led dg834g_leds[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct gpio_led fb_sl_leds[] = {
|
||||
static const struct gpio_led fb_sl_leds[] = {
|
||||
{
|
||||
.name = "1",
|
||||
.gpio = 7,
|
||||
|
|
@ -433,7 +433,7 @@ static struct gpio_led fb_sl_leds[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct gpio_led fb_fon_leds[] = {
|
||||
static const struct gpio_led fb_fon_leds[] = {
|
||||
{
|
||||
.name = "1",
|
||||
.gpio = 8,
|
||||
|
|
@ -459,7 +459,7 @@ static struct gpio_led fb_fon_leds[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct gpio_led gt701_leds[] = {
|
||||
static const struct gpio_led gt701_leds[] = {
|
||||
{
|
||||
.name = "inet:green",
|
||||
.gpio = 13,
|
||||
|
|
|
|||
|
|
@ -355,7 +355,7 @@ bcm47xx_buttons_luxul_xwr_600_v1[] = {
|
|||
|
||||
static const struct gpio_keys_button
|
||||
bcm47xx_buttons_luxul_xwr_1750_v1[] = {
|
||||
BCM47XX_GPIO_KEY(14, BTN_TASK),
|
||||
BCM47XX_GPIO_KEY(14, KEY_RESTART),
|
||||
};
|
||||
|
||||
/* Microsoft */
|
||||
|
|
|
|||
|
|
@ -408,6 +408,12 @@ bcm47xx_leds_luxul_xap_1500_v1[] __initconst = {
|
|||
BCM47XX_GPIO_LED_TRIGGER(13, "green", "status", 1, "timer"),
|
||||
};
|
||||
|
||||
static const struct gpio_led
|
||||
bcm47xx_leds_luxul_xap1500_v1_extra[] __initconst = {
|
||||
BCM47XX_GPIO_LED(44, "green", "5ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
|
||||
BCM47XX_GPIO_LED(76, "green", "2ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
|
||||
};
|
||||
|
||||
static const struct gpio_led
|
||||
bcm47xx_leds_luxul_xbr_4400_v1[] __initconst = {
|
||||
BCM47XX_GPIO_LED(12, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
|
||||
|
|
@ -435,6 +441,11 @@ bcm47xx_leds_luxul_xwr_1750_v1[] __initconst = {
|
|||
BCM47XX_GPIO_LED(15, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
|
||||
};
|
||||
|
||||
static const struct gpio_led
|
||||
bcm47xx_leds_luxul_xwr1750_v1_extra[] __initconst = {
|
||||
BCM47XX_GPIO_LED(76, "green", "2ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
|
||||
};
|
||||
|
||||
/* Microsoft */
|
||||
|
||||
static const struct gpio_led
|
||||
|
|
@ -528,6 +539,12 @@ static struct gpio_led_platform_data bcm47xx_leds_pdata;
|
|||
bcm47xx_leds_pdata.num_leds = ARRAY_SIZE(dev_leds); \
|
||||
} while (0)
|
||||
|
||||
static struct gpio_led_platform_data bcm47xx_leds_pdata_extra __initdata = {};
|
||||
#define bcm47xx_set_pdata_extra(dev_leds) do { \
|
||||
bcm47xx_leds_pdata_extra.leds = dev_leds; \
|
||||
bcm47xx_leds_pdata_extra.num_leds = ARRAY_SIZE(dev_leds); \
|
||||
} while (0)
|
||||
|
||||
void __init bcm47xx_leds_register(void)
|
||||
{
|
||||
enum bcm47xx_board board = bcm47xx_board_get();
|
||||
|
|
@ -705,6 +722,7 @@ void __init bcm47xx_leds_register(void)
|
|||
break;
|
||||
case BCM47XX_BOARD_LUXUL_XAP_1500_V1:
|
||||
bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_1500_v1);
|
||||
bcm47xx_set_pdata_extra(bcm47xx_leds_luxul_xap1500_v1_extra);
|
||||
break;
|
||||
case BCM47XX_BOARD_LUXUL_XBR_4400_V1:
|
||||
bcm47xx_set_pdata(bcm47xx_leds_luxul_xbr_4400_v1);
|
||||
|
|
@ -717,6 +735,7 @@ void __init bcm47xx_leds_register(void)
|
|||
break;
|
||||
case BCM47XX_BOARD_LUXUL_XWR_1750_V1:
|
||||
bcm47xx_set_pdata(bcm47xx_leds_luxul_xwr_1750_v1);
|
||||
bcm47xx_set_pdata_extra(bcm47xx_leds_luxul_xwr1750_v1_extra);
|
||||
break;
|
||||
|
||||
case BCM47XX_BOARD_MICROSOFT_MN700:
|
||||
|
|
@ -760,4 +779,6 @@ void __init bcm47xx_leds_register(void)
|
|||
}
|
||||
|
||||
gpio_led_register_device(-1, &bcm47xx_leds_pdata);
|
||||
if (bcm47xx_leds_pdata_extra.num_leds)
|
||||
gpio_led_register_device(0, &bcm47xx_leds_pdata_extra);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ subdir-y += cavium-octeon
|
|||
subdir-y += img
|
||||
subdir-y += ingenic
|
||||
subdir-y += lantiq
|
||||
subdir-y += mscc
|
||||
subdir-y += mti
|
||||
subdir-y += netlogic
|
||||
subdir-y += ni
|
||||
|
|
|
|||
|
|
@ -198,6 +198,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog: watchdog@4067e8 {
|
||||
clocks = <&upg_clk>;
|
||||
compatible = "brcm,bcm7038-wdt";
|
||||
reg = <0x4067e8 0x14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
upg_gio: gpio@406700 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406700 0x80>;
|
||||
|
|
|
|||
|
|
@ -233,6 +233,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog: watchdog@4067e8 {
|
||||
clocks = <&upg_clk>;
|
||||
compatible = "brcm,bcm7038-wdt";
|
||||
reg = <0x4067e8 0x14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aon_pm_l2_intc: interrupt-controller@408440 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x408440 0x30>;
|
||||
|
|
@ -243,6 +250,17 @@
|
|||
brcm,irq-can-wake;
|
||||
};
|
||||
|
||||
aon_ctrl: syscon@408000 {
|
||||
compatible = "brcm,brcmstb-aon-ctrl";
|
||||
reg = <0x408000 0x100>, <0x408200 0x200>;
|
||||
reg-names = "aon-ctrl", "aon-sram";
|
||||
};
|
||||
|
||||
timers: timer@4067c0 {
|
||||
compatible = "brcm,brcmstb-timers";
|
||||
reg = <0x4067c0 0x40>;
|
||||
};
|
||||
|
||||
upg_gio: gpio@406700 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406700 0x60>;
|
||||
|
|
@ -483,5 +501,49 @@
|
|||
interrupt-names = "mspi_done";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
waketimer: waketimer@408e80 {
|
||||
compatible = "brcm,brcmstb-waketimer";
|
||||
reg = <0x408e80 0x14>;
|
||||
interrupts = <0x3>;
|
||||
interrupt-parent = <&aon_pm_l2_intc>;
|
||||
interrupt-names = "timer";
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
memory_controllers {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x103b0000 0xa000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memory-controller@0 {
|
||||
compatible = "brcm,brcmstb-memc", "simple-bus";
|
||||
ranges = <0x0 0x0 0xa000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memc-arb@1000 {
|
||||
compatible = "brcm,brcmstb-memc-arb";
|
||||
reg = <0x1000 0x248>;
|
||||
};
|
||||
|
||||
memc-ddr@2000 {
|
||||
compatible = "brcm,brcmstb-memc-ddr";
|
||||
reg = <0x2000 0x300>;
|
||||
};
|
||||
|
||||
ddr-phy@6000 {
|
||||
compatible = "brcm,brcmstb-ddr-phy";
|
||||
reg = <0x6000 0xc8>;
|
||||
};
|
||||
|
||||
shimphy@8000 {
|
||||
compatible = "brcm,brcmstb-ddr-shimphy";
|
||||
reg = <0x8000 0x13c>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -217,6 +217,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog: watchdog@4066a8 {
|
||||
clocks = <&upg_clk>;
|
||||
compatible = "brcm,bcm7038-wdt";
|
||||
reg = <0x4066a8 0x14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aon_pm_l2_intc: interrupt-controller@408240 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x408240 0x30>;
|
||||
|
|
@ -362,5 +369,15 @@
|
|||
interrupt-names = "mspi_done";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
waketimer: waketimer@408e80 {
|
||||
compatible = "brcm,brcmstb-waketimer";
|
||||
reg = <0x408e80 0x14>;
|
||||
interrupts = <0x3>;
|
||||
interrupt-parent = <&aon_pm_l2_intc>;
|
||||
interrupt-names = "timer";
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -209,6 +209,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog: watchdog@4066a8 {
|
||||
clocks = <&upg_clk>;
|
||||
compatible = "brcm,bcm7038-wdt";
|
||||
reg = <0x4066a8 0x14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aon_pm_l2_intc: interrupt-controller@408440 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x408440 0x30>;
|
||||
|
|
@ -219,6 +226,17 @@
|
|||
brcm,irq-can-wake;
|
||||
};
|
||||
|
||||
aon_ctrl: syscon@408000 {
|
||||
compatible = "brcm,brcmstb-aon-ctrl";
|
||||
reg = <0x408000 0x100>, <0x408200 0x200>;
|
||||
reg-names = "aon-ctrl", "aon-sram";
|
||||
};
|
||||
|
||||
timers: timer@406680 {
|
||||
compatible = "brcm,brcmstb-timers";
|
||||
reg = <0x406680 0x40>;
|
||||
};
|
||||
|
||||
upg_gio: gpio@406500 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406500 0xa0>;
|
||||
|
|
@ -402,5 +420,49 @@
|
|||
interrupt-names = "mspi_done";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
waketimer: waketimer@408e80 {
|
||||
compatible = "brcm,brcmstb-waketimer";
|
||||
reg = <0x408e80 0x14>;
|
||||
interrupts = <0x3>;
|
||||
interrupt-parent = <&aon_pm_l2_intc>;
|
||||
interrupt-names = "timer";
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
memory_controllers {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x103b0000 0xa000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memory-controller@0 {
|
||||
compatible = "brcm,brcmstb-memc", "simple-bus";
|
||||
ranges = <0x0 0x0 0xa000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memc-arb@1000 {
|
||||
compatible = "brcm,brcmstb-memc-arb";
|
||||
reg = <0x1000 0x248>;
|
||||
};
|
||||
|
||||
memc-ddr@2000 {
|
||||
compatible = "brcm,brcmstb-memc-ddr";
|
||||
reg = <0x2000 0x300>;
|
||||
};
|
||||
|
||||
ddr-phy@6000 {
|
||||
compatible = "brcm,brcmstb-ddr-phy";
|
||||
reg = <0x6000 0xc8>;
|
||||
};
|
||||
|
||||
shimphy@8000 {
|
||||
compatible = "brcm,brcmstb-ddr-shimphy";
|
||||
reg = <0x8000 0x13c>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -205,6 +205,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog: watchdog@4066a8 {
|
||||
clocks = <&upg_clk>;
|
||||
compatible = "brcm,bcm7038-wdt";
|
||||
reg = <0x4066a8 0x14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aon_pm_l2_intc: interrupt-controller@408440 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x408440 0x30>;
|
||||
|
|
@ -215,6 +222,17 @@
|
|||
brcm,irq-can-wake;
|
||||
};
|
||||
|
||||
aon_ctrl: syscon@408000 {
|
||||
compatible = "brcm,brcmstb-aon-ctrl";
|
||||
reg = <0x408000 0x100>, <0x408200 0x200>;
|
||||
reg-names = "aon-ctrl", "aon-sram";
|
||||
};
|
||||
|
||||
timers: timer@406680 {
|
||||
compatible = "brcm,brcmstb-timers";
|
||||
reg = <0x406680 0x40>;
|
||||
};
|
||||
|
||||
upg_gio: gpio@406500 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406500 0xa0>;
|
||||
|
|
@ -398,5 +416,49 @@
|
|||
interrupt-names = "mspi_done";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
waketimer: waketimer@408e80 {
|
||||
compatible = "brcm,brcmstb-waketimer";
|
||||
reg = <0x408e80 0x14>;
|
||||
interrupts = <0x3>;
|
||||
interrupt-parent = <&aon_pm_l2_intc>;
|
||||
interrupt-names = "timer";
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
memory_controllers {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x103b0000 0xa000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memory-controller@0 {
|
||||
compatible = "brcm,brcmstb-memc", "simple-bus";
|
||||
ranges = <0x0 0x0 0xa000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memc-arb@1000 {
|
||||
compatible = "brcm,brcmstb-memc-arb";
|
||||
reg = <0x1000 0x248>;
|
||||
};
|
||||
|
||||
memc-ddr@2000 {
|
||||
compatible = "brcm,brcmstb-memc-ddr";
|
||||
reg = <0x2000 0x300>;
|
||||
};
|
||||
|
||||
ddr-phy@6000 {
|
||||
compatible = "brcm,brcmstb-ddr-phy";
|
||||
reg = <0x6000 0xc8>;
|
||||
};
|
||||
|
||||
shimphy@8000 {
|
||||
compatible = "brcm,brcmstb-ddr-shimphy";
|
||||
reg = <0x8000 0x13c>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -214,6 +214,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog: watchdog@4067e8 {
|
||||
clocks = <&upg_clk>;
|
||||
compatible = "brcm,bcm7038-wdt";
|
||||
reg = <0x4067e8 0x14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
upg_gio: gpio@406700 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406700 0x80>;
|
||||
|
|
|
|||
|
|
@ -232,6 +232,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog: watchdog@4067e8 {
|
||||
clocks = <&upg_clk>;
|
||||
compatible = "brcm,bcm7038-wdt";
|
||||
reg = <0x4067e8 0x14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aon_pm_l2_intc: interrupt-controller@408440 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x408440 0x30>;
|
||||
|
|
@ -242,6 +249,17 @@
|
|||
brcm,irq-can-wake;
|
||||
};
|
||||
|
||||
aon_ctrl: syscon@408000 {
|
||||
compatible = "brcm,brcmstb-aon-ctrl";
|
||||
reg = <0x408000 0x100>, <0x408200 0x200>;
|
||||
reg-names = "aon-ctrl", "aon-sram";
|
||||
};
|
||||
|
||||
timers: timer@4067c0 {
|
||||
compatible = "brcm,brcmstb-timers";
|
||||
reg = <0x4067c0 0x40>;
|
||||
};
|
||||
|
||||
upg_gio: gpio@406700 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406700 0x80>;
|
||||
|
|
@ -494,5 +512,76 @@
|
|||
interrupt-names = "mspi_done";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
waketimer: waketimer@409580 {
|
||||
compatible = "brcm,brcmstb-waketimer";
|
||||
reg = <0x409580 0x14>;
|
||||
interrupts = <0x3>;
|
||||
interrupt-parent = <&aon_pm_l2_intc>;
|
||||
interrupt-names = "timer";
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
memory_controllers {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x103b0000 0x1a000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memory-controller@0 {
|
||||
compatible = "brcm,brcmstb-memc", "simple-bus";
|
||||
ranges = <0x0 0x0 0xa000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memc-arb@1000 {
|
||||
compatible = "brcm,brcmstb-memc-arb";
|
||||
reg = <0x1000 0x248>;
|
||||
};
|
||||
|
||||
memc-ddr@2000 {
|
||||
compatible = "brcm,brcmstb-memc-ddr";
|
||||
reg = <0x2000 0x300>;
|
||||
};
|
||||
|
||||
ddr-phy@6000 {
|
||||
compatible = "brcm,brcmstb-ddr-phy";
|
||||
reg = <0x6000 0xc8>;
|
||||
};
|
||||
|
||||
shimphy@8000 {
|
||||
compatible = "brcm,brcmstb-ddr-shimphy";
|
||||
reg = <0x8000 0x13c>;
|
||||
};
|
||||
};
|
||||
|
||||
memory-controller@1 {
|
||||
compatible = "brcm,brcmstb-memc", "simple-bus";
|
||||
ranges = <0x0 0x10000 0xa000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memc-arb@1000 {
|
||||
compatible = "brcm,brcmstb-memc-arb";
|
||||
reg = <0x1000 0x248>;
|
||||
};
|
||||
|
||||
memc-ddr@2000 {
|
||||
compatible = "brcm,brcmstb-memc-ddr";
|
||||
reg = <0x2000 0x300>;
|
||||
};
|
||||
|
||||
ddr-phy@6000 {
|
||||
compatible = "brcm,brcmstb-ddr-phy";
|
||||
reg = <0x6000 0xc8>;
|
||||
};
|
||||
|
||||
shimphy@8000 {
|
||||
compatible = "brcm,brcmstb-ddr-shimphy";
|
||||
reg = <0x8000 0x13c>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -247,6 +247,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog: watchdog@4067e8 {
|
||||
clocks = <&upg_clk>;
|
||||
compatible = "brcm,bcm7038-wdt";
|
||||
reg = <0x4067e8 0x14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aon_pm_l2_intc: interrupt-controller@408440 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x408440 0x30>;
|
||||
|
|
@ -257,6 +264,17 @@
|
|||
brcm,irq-can-wake;
|
||||
};
|
||||
|
||||
aon_ctrl: syscon@408000 {
|
||||
compatible = "brcm,brcmstb-aon-ctrl";
|
||||
reg = <0x408000 0x100>, <0x408200 0x200>;
|
||||
reg-names = "aon-ctrl", "aon-sram";
|
||||
};
|
||||
|
||||
timers: timer@4067c0 {
|
||||
compatible = "brcm,brcmstb-timers";
|
||||
reg = <0x4067c0 0x40>;
|
||||
};
|
||||
|
||||
upg_gio: gpio@406700 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406700 0x80>;
|
||||
|
|
@ -509,5 +527,76 @@
|
|||
interrupt-names = "mspi_done";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
waketimer: waketimer@409580 {
|
||||
compatible = "brcm,brcmstb-waketimer";
|
||||
reg = <0x409580 0x14>;
|
||||
interrupts = <0x3>;
|
||||
interrupt-parent = <&aon_pm_l2_intc>;
|
||||
interrupt-names = "timer";
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
memory_controllers {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x103b0000 0x1a000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memory-controller@0 {
|
||||
compatible = "brcm,brcmstb-memc", "simple-bus";
|
||||
ranges = <0x0 0x0 0xa000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memc-arb@1000 {
|
||||
compatible = "brcm,brcmstb-memc-arb";
|
||||
reg = <0x1000 0x248>;
|
||||
};
|
||||
|
||||
memc-ddr@2000 {
|
||||
compatible = "brcm,brcmstb-memc-ddr";
|
||||
reg = <0x2000 0x300>;
|
||||
};
|
||||
|
||||
ddr-phy@6000 {
|
||||
compatible = "brcm,brcmstb-ddr-phy";
|
||||
reg = <0x6000 0xc8>;
|
||||
};
|
||||
|
||||
shimphy@8000 {
|
||||
compatible = "brcm,brcmstb-ddr-shimphy";
|
||||
reg = <0x8000 0x13c>;
|
||||
};
|
||||
};
|
||||
|
||||
memory-controller@1 {
|
||||
compatible = "brcm,brcmstb-memc", "simple-bus";
|
||||
ranges = <0x0 0x10000 0xa000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
memc-arb@1000 {
|
||||
compatible = "brcm,brcmstb-memc-arb";
|
||||
reg = <0x1000 0x248>;
|
||||
};
|
||||
|
||||
memc-ddr@2000 {
|
||||
compatible = "brcm,brcmstb-memc-ddr";
|
||||
reg = <0x2000 0x300>;
|
||||
};
|
||||
|
||||
ddr-phy@6000 {
|
||||
compatible = "brcm,brcmstb-ddr-phy";
|
||||
reg = <0x6000 0xc8>;
|
||||
};
|
||||
|
||||
shimphy@8000 {
|
||||
compatible = "brcm,brcmstb-ddr-shimphy";
|
||||
reg = <0x8000 0x13c>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -50,6 +50,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* FIXME: USB is wonky; disable it for now */
|
||||
&ehci0 {
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -59,6 +59,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -114,3 +118,7 @@
|
|||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&waketimer {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -55,6 +55,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -106,3 +110,7 @@
|
|||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&waketimer {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -50,6 +50,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -109,3 +113,7 @@
|
|||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&waketimer {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -47,6 +47,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -78,3 +82,7 @@
|
|||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&waketimer {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -60,6 +60,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* FIXME: MAC driver comes up but cannot attach to PHY */
|
||||
&enet0 {
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -61,6 +61,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -144,3 +148,7 @@
|
|||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&waketimer {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -61,6 +61,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -120,3 +124,7 @@
|
|||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&waketimer {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -157,7 +157,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtc@0x68 {
|
||||
rtc@68 {
|
||||
compatible = "st,m41t81s";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -110,22 +110,22 @@
|
|||
reg = <0x0 0x0 0x0 0x800000>;
|
||||
};
|
||||
|
||||
partition@0x800000 {
|
||||
partition@800000 {
|
||||
label = "u-boot";
|
||||
reg = <0x0 0x800000 0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@0xa00000 {
|
||||
partition@a00000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x0 0xa00000 0x0 0x200000>;
|
||||
};
|
||||
|
||||
partition@0xc00000 {
|
||||
partition@c00000 {
|
||||
label = "boot";
|
||||
reg = <0x0 0xc00000 0x0 0x4000000>;
|
||||
};
|
||||
|
||||
partition@0x8c00000 {
|
||||
partition@4c00000 {
|
||||
label = "system";
|
||||
reg = <0x0 0x4c00000 0x1 0xfb400000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
dtb-$(CONFIG_LEGACY_BOARD_OCELOT) += ocelot_pcb123.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/* Copyright (c) 2017 Microsemi Corporation */
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mscc,ocelot";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "mips,mips24KEc";
|
||||
device_type = "cpu";
|
||||
clocks = <&cpu_clk>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
cpuintc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
cpu_clk: cpu-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <500000000>;
|
||||
};
|
||||
|
||||
ahb_clk: ahb-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&cpu_clk>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
|
||||
ahb@70000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x70000000 0x2000000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpu_ctrl: syscon@0 {
|
||||
compatible = "mscc,ocelot-cpu-syscon", "syscon";
|
||||
reg = <0x0 0x2c>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@70 {
|
||||
compatible = "mscc,ocelot-icpu-intr";
|
||||
reg = <0x70 0x70>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
uart0: serial@100000 {
|
||||
pinctrl-0 = <&uart_pins>;
|
||||
pinctrl-names = "default";
|
||||
compatible = "ns16550a";
|
||||
reg = <0x100000 0x20>;
|
||||
interrupts = <6>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@100800 {
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
compatible = "ns16550a";
|
||||
reg = <0x100800 0x20>;
|
||||
interrupts = <7>;
|
||||
clocks = <&ahb_clk>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
reset@1070008 {
|
||||
compatible = "mscc,ocelot-chip-reset";
|
||||
reg = <0x1070008 0x4>;
|
||||
};
|
||||
|
||||
gpio: pinctrl@1070034 {
|
||||
compatible = "mscc,ocelot-pinctrl";
|
||||
reg = <0x1070034 0x68>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&gpio 0 0 22>;
|
||||
|
||||
uart_pins: uart-pins {
|
||||
pins = "GPIO_6", "GPIO_7";
|
||||
function = "uart";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
pins = "GPIO_12", "GPIO_13";
|
||||
function = "uart2";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/* Copyright (c) 2017 Microsemi Corporation */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ocelot.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0e000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -2271,7 +2271,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
|
|||
|
||||
parent_irq = irq_of_parse_and_map(ciu_node, 0);
|
||||
if (!parent_irq) {
|
||||
pr_err("ERROR: Couldn't acquire parent_irq for %s\n.",
|
||||
pr_err("ERROR: Couldn't acquire parent_irq for %s\n",
|
||||
ciu_node->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -2283,7 +2283,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
|
|||
|
||||
addr = of_get_address(ciu_node, 0, NULL, NULL);
|
||||
if (!addr) {
|
||||
pr_err("ERROR: Couldn't acquire reg(0) %s\n.", ciu_node->name);
|
||||
pr_err("ERROR: Couldn't acquire reg(0) %s\n", ciu_node->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
host_data->raw_reg = (u64)phys_to_virt(
|
||||
|
|
@ -2291,7 +2291,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
|
|||
|
||||
addr = of_get_address(ciu_node, 1, NULL, NULL);
|
||||
if (!addr) {
|
||||
pr_err("ERROR: Couldn't acquire reg(1) %s\n.", ciu_node->name);
|
||||
pr_err("ERROR: Couldn't acquire reg(1) %s\n", ciu_node->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
host_data->en_reg = (u64)phys_to_virt(
|
||||
|
|
@ -2299,7 +2299,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
|
|||
|
||||
r = of_property_read_u32(ciu_node, "cavium,max-bits", &val);
|
||||
if (r) {
|
||||
pr_err("ERROR: Couldn't read cavium,max-bits from %s\n.",
|
||||
pr_err("ERROR: Couldn't read cavium,max-bits from %s\n",
|
||||
ciu_node->name);
|
||||
return r;
|
||||
}
|
||||
|
|
@ -2309,7 +2309,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
|
|||
&octeon_irq_domain_cib_ops,
|
||||
host_data);
|
||||
if (!cib_domain) {
|
||||
pr_err("ERROR: Couldn't irq_domain_add_linear()\n.");
|
||||
pr_err("ERROR: Couldn't irq_domain_add_linear()\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -72,6 +72,7 @@ CONFIG_USB_EHCI_HCD_PLATFORM=y
|
|||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SOC_BRCMSTB=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
|
|
|
|||
|
|
@ -1,2 +1,4 @@
|
|||
CONFIG_CPU_MIPS32_R6=y
|
||||
CONFIG_HIGHMEM=y
|
||||
|
||||
CONFIG_CRYPTO_CRC32_MIPS=y
|
||||
|
|
|
|||
|
|
@ -2,3 +2,5 @@ CONFIG_CPU_MIPS64_R6=y
|
|||
CONFIG_64BIT=y
|
||||
CONFIG_MIPS32_O32=y
|
||||
CONFIG_MIPS32_N32=y
|
||||
|
||||
CONFIG_CRYPTO_CRC32_MIPS=y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,35 @@
|
|||
# require CONFIG_CPU_MIPS32_R2=y
|
||||
|
||||
CONFIG_LEGACY_BOARD_OCELOT=y
|
||||
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_PLATFORM=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_UBI=y
|
||||
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MUX=y
|
||||
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_DESIGNWARE=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_OCELOT_RESET=y
|
||||
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# Makefile for MIPS crypto files..
|
||||
#
|
||||
|
||||
obj-$(CONFIG_CRYPTO_CRC32_MIPS) += crc32-mips.o
|
||||
|
|
@ -0,0 +1,348 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* crc32-mips.c - CRC32 and CRC32C using optional MIPSr6 instructions
|
||||
*
|
||||
* Module based on arm64/crypto/crc32-arm.c
|
||||
*
|
||||
* Copyright (C) 2014 Linaro Ltd <yazen.ghannam@linaro.org>
|
||||
* Copyright (C) 2018 MIPS Tech, LLC
|
||||
*/
|
||||
|
||||
#include <linux/unaligned/access_ok.h>
|
||||
#include <linux/cpufeature.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/string.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
#include <crypto/internal/hash.h>
|
||||
|
||||
enum crc_op_size {
|
||||
b, h, w, d,
|
||||
};
|
||||
|
||||
enum crc_type {
|
||||
crc32,
|
||||
crc32c,
|
||||
};
|
||||
|
||||
#ifndef TOOLCHAIN_SUPPORTS_CRC
|
||||
#define _ASM_MACRO_CRC32(OP, SZ, TYPE) \
|
||||
_ASM_MACRO_3R(OP, rt, rs, rt2, \
|
||||
".ifnc \\rt, \\rt2\n\t" \
|
||||
".error \"invalid operands \\\"" #OP " \\rt,\\rs,\\rt2\\\"\"\n\t" \
|
||||
".endif\n\t" \
|
||||
_ASM_INSN_IF_MIPS(0x7c00000f | (__rt << 16) | (__rs << 21) | \
|
||||
((SZ) << 6) | ((TYPE) << 8)) \
|
||||
_ASM_INSN32_IF_MM(0x00000030 | (__rs << 16) | (__rt << 21) | \
|
||||
((SZ) << 14) | ((TYPE) << 3)))
|
||||
_ASM_MACRO_CRC32(crc32b, 0, 0);
|
||||
_ASM_MACRO_CRC32(crc32h, 1, 0);
|
||||
_ASM_MACRO_CRC32(crc32w, 2, 0);
|
||||
_ASM_MACRO_CRC32(crc32d, 3, 0);
|
||||
_ASM_MACRO_CRC32(crc32cb, 0, 1);
|
||||
_ASM_MACRO_CRC32(crc32ch, 1, 1);
|
||||
_ASM_MACRO_CRC32(crc32cw, 2, 1);
|
||||
_ASM_MACRO_CRC32(crc32cd, 3, 1);
|
||||
#define _ASM_SET_CRC ""
|
||||
#else /* !TOOLCHAIN_SUPPORTS_CRC */
|
||||
#define _ASM_SET_CRC ".set\tcrc\n\t"
|
||||
#endif
|
||||
|
||||
#define _CRC32(crc, value, size, type) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
".set push\n\t" \
|
||||
_ASM_SET_CRC \
|
||||
#type #size " %0, %1, %0\n\t" \
|
||||
".set pop" \
|
||||
: "+r" (crc) \
|
||||
: "r" (value)); \
|
||||
} while (0)
|
||||
|
||||
#define CRC32(crc, value, size) \
|
||||
_CRC32(crc, value, size, crc32)
|
||||
|
||||
#define CRC32C(crc, value, size) \
|
||||
_CRC32(crc, value, size, crc32c)
|
||||
|
||||
static u32 crc32_mips_le_hw(u32 crc_, const u8 *p, unsigned int len)
|
||||
{
|
||||
u32 crc = crc_;
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
while (len >= sizeof(u64)) {
|
||||
u64 value = get_unaligned_le64(p);
|
||||
|
||||
CRC32(crc, value, d);
|
||||
p += sizeof(u64);
|
||||
len -= sizeof(u64);
|
||||
}
|
||||
|
||||
if (len & sizeof(u32)) {
|
||||
#else /* !CONFIG_64BIT */
|
||||
while (len >= sizeof(u32)) {
|
||||
#endif
|
||||
u32 value = get_unaligned_le32(p);
|
||||
|
||||
CRC32(crc, value, w);
|
||||
p += sizeof(u32);
|
||||
len -= sizeof(u32);
|
||||
}
|
||||
|
||||
if (len & sizeof(u16)) {
|
||||
u16 value = get_unaligned_le16(p);
|
||||
|
||||
CRC32(crc, value, h);
|
||||
p += sizeof(u16);
|
||||
}
|
||||
|
||||
if (len & sizeof(u8)) {
|
||||
u8 value = *p++;
|
||||
|
||||
CRC32(crc, value, b);
|
||||
}
|
||||
|
||||
return crc;
|
||||
}
|
||||
|
||||
static u32 crc32c_mips_le_hw(u32 crc_, const u8 *p, unsigned int len)
|
||||
{
|
||||
u32 crc = crc_;
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
while (len >= sizeof(u64)) {
|
||||
u64 value = get_unaligned_le64(p);
|
||||
|
||||
CRC32C(crc, value, d);
|
||||
p += sizeof(u64);
|
||||
len -= sizeof(u64);
|
||||
}
|
||||
|
||||
if (len & sizeof(u32)) {
|
||||
#else /* !CONFIG_64BIT */
|
||||
while (len >= sizeof(u32)) {
|
||||
#endif
|
||||
u32 value = get_unaligned_le32(p);
|
||||
|
||||
CRC32C(crc, value, w);
|
||||
p += sizeof(u32);
|
||||
len -= sizeof(u32);
|
||||
}
|
||||
|
||||
if (len & sizeof(u16)) {
|
||||
u16 value = get_unaligned_le16(p);
|
||||
|
||||
CRC32C(crc, value, h);
|
||||
p += sizeof(u16);
|
||||
}
|
||||
|
||||
if (len & sizeof(u8)) {
|
||||
u8 value = *p++;
|
||||
|
||||
CRC32C(crc, value, b);
|
||||
}
|
||||
return crc;
|
||||
}
|
||||
|
||||
#define CHKSUM_BLOCK_SIZE 1
|
||||
#define CHKSUM_DIGEST_SIZE 4
|
||||
|
||||
struct chksum_ctx {
|
||||
u32 key;
|
||||
};
|
||||
|
||||
struct chksum_desc_ctx {
|
||||
u32 crc;
|
||||
};
|
||||
|
||||
static int chksum_init(struct shash_desc *desc)
|
||||
{
|
||||
struct chksum_ctx *mctx = crypto_shash_ctx(desc->tfm);
|
||||
struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
|
||||
|
||||
ctx->crc = mctx->key;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Setting the seed allows arbitrary accumulators and flexible XOR policy
|
||||
* If your algorithm starts with ~0, then XOR with ~0 before you set
|
||||
* the seed.
|
||||
*/
|
||||
static int chksum_setkey(struct crypto_shash *tfm, const u8 *key,
|
||||
unsigned int keylen)
|
||||
{
|
||||
struct chksum_ctx *mctx = crypto_shash_ctx(tfm);
|
||||
|
||||
if (keylen != sizeof(mctx->key)) {
|
||||
crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
||||
return -EINVAL;
|
||||
}
|
||||
mctx->key = get_unaligned_le32(key);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int chksum_update(struct shash_desc *desc, const u8 *data,
|
||||
unsigned int length)
|
||||
{
|
||||
struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
|
||||
|
||||
ctx->crc = crc32_mips_le_hw(ctx->crc, data, length);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int chksumc_update(struct shash_desc *desc, const u8 *data,
|
||||
unsigned int length)
|
||||
{
|
||||
struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
|
||||
|
||||
ctx->crc = crc32c_mips_le_hw(ctx->crc, data, length);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int chksum_final(struct shash_desc *desc, u8 *out)
|
||||
{
|
||||
struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
|
||||
|
||||
put_unaligned_le32(ctx->crc, out);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int chksumc_final(struct shash_desc *desc, u8 *out)
|
||||
{
|
||||
struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
|
||||
|
||||
put_unaligned_le32(~ctx->crc, out);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __chksum_finup(u32 crc, const u8 *data, unsigned int len, u8 *out)
|
||||
{
|
||||
put_unaligned_le32(crc32_mips_le_hw(crc, data, len), out);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __chksumc_finup(u32 crc, const u8 *data, unsigned int len, u8 *out)
|
||||
{
|
||||
put_unaligned_le32(~crc32c_mips_le_hw(crc, data, len), out);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int chksum_finup(struct shash_desc *desc, const u8 *data,
|
||||
unsigned int len, u8 *out)
|
||||
{
|
||||
struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
|
||||
|
||||
return __chksum_finup(ctx->crc, data, len, out);
|
||||
}
|
||||
|
||||
static int chksumc_finup(struct shash_desc *desc, const u8 *data,
|
||||
unsigned int len, u8 *out)
|
||||
{
|
||||
struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
|
||||
|
||||
return __chksumc_finup(ctx->crc, data, len, out);
|
||||
}
|
||||
|
||||
static int chksum_digest(struct shash_desc *desc, const u8 *data,
|
||||
unsigned int length, u8 *out)
|
||||
{
|
||||
struct chksum_ctx *mctx = crypto_shash_ctx(desc->tfm);
|
||||
|
||||
return __chksum_finup(mctx->key, data, length, out);
|
||||
}
|
||||
|
||||
static int chksumc_digest(struct shash_desc *desc, const u8 *data,
|
||||
unsigned int length, u8 *out)
|
||||
{
|
||||
struct chksum_ctx *mctx = crypto_shash_ctx(desc->tfm);
|
||||
|
||||
return __chksumc_finup(mctx->key, data, length, out);
|
||||
}
|
||||
|
||||
static int chksum_cra_init(struct crypto_tfm *tfm)
|
||||
{
|
||||
struct chksum_ctx *mctx = crypto_tfm_ctx(tfm);
|
||||
|
||||
mctx->key = ~0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct shash_alg crc32_alg = {
|
||||
.digestsize = CHKSUM_DIGEST_SIZE,
|
||||
.setkey = chksum_setkey,
|
||||
.init = chksum_init,
|
||||
.update = chksum_update,
|
||||
.final = chksum_final,
|
||||
.finup = chksum_finup,
|
||||
.digest = chksum_digest,
|
||||
.descsize = sizeof(struct chksum_desc_ctx),
|
||||
.base = {
|
||||
.cra_name = "crc32",
|
||||
.cra_driver_name = "crc32-mips-hw",
|
||||
.cra_priority = 300,
|
||||
.cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
|
||||
.cra_blocksize = CHKSUM_BLOCK_SIZE,
|
||||
.cra_alignmask = 0,
|
||||
.cra_ctxsize = sizeof(struct chksum_ctx),
|
||||
.cra_module = THIS_MODULE,
|
||||
.cra_init = chksum_cra_init,
|
||||
}
|
||||
};
|
||||
|
||||
static struct shash_alg crc32c_alg = {
|
||||
.digestsize = CHKSUM_DIGEST_SIZE,
|
||||
.setkey = chksum_setkey,
|
||||
.init = chksum_init,
|
||||
.update = chksumc_update,
|
||||
.final = chksumc_final,
|
||||
.finup = chksumc_finup,
|
||||
.digest = chksumc_digest,
|
||||
.descsize = sizeof(struct chksum_desc_ctx),
|
||||
.base = {
|
||||
.cra_name = "crc32c",
|
||||
.cra_driver_name = "crc32c-mips-hw",
|
||||
.cra_priority = 300,
|
||||
.cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
|
||||
.cra_blocksize = CHKSUM_BLOCK_SIZE,
|
||||
.cra_alignmask = 0,
|
||||
.cra_ctxsize = sizeof(struct chksum_ctx),
|
||||
.cra_module = THIS_MODULE,
|
||||
.cra_init = chksum_cra_init,
|
||||
}
|
||||
};
|
||||
|
||||
static int __init crc32_mod_init(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = crypto_register_shash(&crc32_alg);
|
||||
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = crypto_register_shash(&crc32c_alg);
|
||||
|
||||
if (err) {
|
||||
crypto_unregister_shash(&crc32_alg);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit crc32_mod_exit(void)
|
||||
{
|
||||
crypto_unregister_shash(&crc32_alg);
|
||||
crypto_unregister_shash(&crc32c_alg);
|
||||
}
|
||||
|
||||
MODULE_AUTHOR("Marcin Nowakowski <marcin.nowakowski@mips.com");
|
||||
MODULE_DESCRIPTION("CRC32 and CRC32C using optional MIPS instructions");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
module_cpu_feature_match(MIPS_CRC32, crc32_mod_init);
|
||||
module_exit(crc32_mod_exit);
|
||||
|
|
@ -27,6 +27,22 @@ config LEGACY_BOARD_SEAD3
|
|||
Enable this to include support for booting on MIPS SEAD-3 FPGA-based
|
||||
development boards, which boot using a legacy boot protocol.
|
||||
|
||||
comment "MSCC Ocelot doesn't work with SEAD3 enabled"
|
||||
depends on LEGACY_BOARD_SEAD3
|
||||
|
||||
config LEGACY_BOARD_OCELOT
|
||||
bool "Support MSCC Ocelot boards"
|
||||
depends on LEGACY_BOARD_SEAD3=n
|
||||
select LEGACY_BOARDS
|
||||
select MSCC_OCELOT
|
||||
|
||||
config MSCC_OCELOT
|
||||
bool
|
||||
select GPIOLIB
|
||||
select MSCC_OCELOT_IRQ
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select USE_GENERIC_EARLY_PRINTK_8250
|
||||
|
||||
comment "FIT/UHI Boards"
|
||||
|
||||
config FIT_IMAGE_FDT_BOSTON
|
||||
|
|
|
|||
|
|
@ -14,5 +14,6 @@ obj-y += proc.o
|
|||
|
||||
obj-$(CONFIG_YAMON_DT_SHIM) += yamon-dt.o
|
||||
obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o
|
||||
obj-$(CONFIG_LEGACY_BOARD_OCELOT) += board-ocelot.o
|
||||
obj-$(CONFIG_KEXEC) += kexec.o
|
||||
obj-$(CONFIG_VIRT_BOARD_RANCHU) += board-ranchu.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,78 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Microsemi MIPS SoC support
|
||||
*
|
||||
* Copyright (c) 2017 Microsemi Corporation
|
||||
*/
|
||||
#include <asm/machine.h>
|
||||
#include <asm/prom.h>
|
||||
|
||||
#define DEVCPU_GCB_CHIP_REGS_CHIP_ID 0x71070000
|
||||
#define CHIP_ID_PART_ID GENMASK(27, 12)
|
||||
|
||||
#define OCELOT_PART_ID (0x7514 << 12)
|
||||
|
||||
#define UART_UART 0x70100000
|
||||
|
||||
static __init bool ocelot_detect(void)
|
||||
{
|
||||
u32 rev;
|
||||
int idx;
|
||||
|
||||
/* Look for the TLB entry set up by redboot before trying to use it */
|
||||
write_c0_entryhi(DEVCPU_GCB_CHIP_REGS_CHIP_ID);
|
||||
mtc0_tlbw_hazard();
|
||||
tlb_probe();
|
||||
tlb_probe_hazard();
|
||||
idx = read_c0_index();
|
||||
if (idx < 0)
|
||||
return 0;
|
||||
|
||||
/* A TLB entry exists, lets assume its usable and check the CHIP ID */
|
||||
rev = __raw_readl((void __iomem *)DEVCPU_GCB_CHIP_REGS_CHIP_ID);
|
||||
|
||||
if ((rev & CHIP_ID_PART_ID) != OCELOT_PART_ID)
|
||||
return 0;
|
||||
|
||||
/* Copy command line from bootloader early for Initrd detection */
|
||||
if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) {
|
||||
unsigned int prom_argc = fw_arg0;
|
||||
const char **prom_argv = (const char **)fw_arg1;
|
||||
|
||||
if (prom_argc > 1 && strlen(prom_argv[1]) > 0)
|
||||
/* ignore all built-in args if any f/w args given */
|
||||
strcpy(arcs_cmdline, prom_argv[1]);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void __init ocelot_earlyprintk_init(void)
|
||||
{
|
||||
void __iomem *uart_base;
|
||||
|
||||
uart_base = ioremap_nocache(UART_UART, 0x20);
|
||||
setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000);
|
||||
}
|
||||
|
||||
static void __init ocelot_late_init(void)
|
||||
{
|
||||
ocelot_earlyprintk_init();
|
||||
}
|
||||
|
||||
static __init const void *ocelot_fixup_fdt(const void *fdt,
|
||||
const void *match_data)
|
||||
{
|
||||
/* This has to be done so late because ioremap needs to work */
|
||||
late_time_init = ocelot_late_init;
|
||||
|
||||
return fdt;
|
||||
}
|
||||
|
||||
extern char __dtb_ocelot_pcb123_begin[];
|
||||
|
||||
MIPS_MACHINE(ocelot) = {
|
||||
.fdt = __dtb_ocelot_pcb123_begin,
|
||||
.fixup_fdt = ocelot_fixup_fdt,
|
||||
.detect = ocelot_detect,
|
||||
};
|
||||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cpu-info.h>
|
||||
#include <asm/isa-rev.h>
|
||||
#include <cpu-feature-overrides.h>
|
||||
|
||||
/*
|
||||
|
|
@ -493,7 +494,7 @@
|
|||
# define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
|
||||
#if defined(CONFIG_SMP) && (MIPS_ISA_REV >= 6)
|
||||
/*
|
||||
* Some systems share FTLB RAMs between threads within a core (siblings in
|
||||
* kernel parlance). This means that FTLB entries may become invalid at almost
|
||||
|
|
@ -525,7 +526,7 @@
|
|||
# define cpu_has_shared_ftlb_entries \
|
||||
(current_cpu_data.options & MIPS_CPU_SHARED_FTLB_ENTRIES)
|
||||
# endif
|
||||
#endif /* SMP && __mips_isa_rev >= 6 */
|
||||
#endif /* SMP && MIPS_ISA_REV >= 6 */
|
||||
|
||||
#ifndef cpu_has_shared_ftlb_ram
|
||||
# define cpu_has_shared_ftlb_ram 0
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 MIPS Tech, LLC
|
||||
* Author: Matt Redfearn <matt.redfearn@mips.com>
|
||||
*/
|
||||
|
||||
#ifndef __MIPS_ASM_ISA_REV_H__
|
||||
#define __MIPS_ASM_ISA_REV_H__
|
||||
|
||||
/*
|
||||
* The ISA revision level. This is 0 for MIPS I to V and N for
|
||||
* MIPS{32,64}rN.
|
||||
*/
|
||||
|
||||
/* If the compiler has defined __mips_isa_rev, believe it. */
|
||||
#ifdef __mips_isa_rev
|
||||
#define MIPS_ISA_REV __mips_isa_rev
|
||||
#else
|
||||
/* The compiler hasn't defined the isa rev so assume it's MIPS I - V (0) */
|
||||
#define MIPS_ISA_REV 0
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __MIPS_ASM_ISA_REV_H__ */
|
||||
|
|
@ -167,7 +167,7 @@
|
|||
#define AR71XX_AHB_DIV_MASK 0x7
|
||||
|
||||
#define AR724X_PLL_REG_CPU_CONFIG 0x00
|
||||
#define AR724X_PLL_REG_PCIE_CONFIG 0x18
|
||||
#define AR724X_PLL_REG_PCIE_CONFIG 0x10
|
||||
|
||||
#define AR724X_PLL_FB_SHIFT 0
|
||||
#define AR724X_PLL_FB_MASK 0x3ff
|
||||
|
|
|
|||
|
|
@ -664,6 +664,7 @@
|
|||
#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
|
||||
#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
|
||||
#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
|
||||
#define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
|
||||
#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
|
||||
#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
|
||||
#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
|
||||
|
|
|
|||
|
|
@ -5,5 +5,6 @@
|
|||
/* HWCAP flags */
|
||||
#define HWCAP_MIPS_R6 (1 << 0)
|
||||
#define HWCAP_MIPS_MSA (1 << 1)
|
||||
#define HWCAP_MIPS_CRC32 (1 << 2)
|
||||
|
||||
#endif /* _UAPI_ASM_HWCAP_H */
|
||||
|
|
|
|||
|
|
@ -848,6 +848,9 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
|
|||
if (config5 & MIPS_CONF5_CA2)
|
||||
c->ases |= MIPS_ASE_MIPS16E2;
|
||||
|
||||
if (config5 & MIPS_CONF5_CRCP)
|
||||
elf_hwcap |= HWCAP_MIPS_CRC32;
|
||||
|
||||
return config5 & MIPS_CONF_M;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/percpu.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/suspend.h>
|
||||
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
|
@ -670,6 +671,34 @@ static int cps_pm_online_cpu(unsigned int cpu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int cps_pm_power_notifier(struct notifier_block *this,
|
||||
unsigned long event, void *ptr)
|
||||
{
|
||||
unsigned int stat;
|
||||
|
||||
switch (event) {
|
||||
case PM_SUSPEND_PREPARE:
|
||||
stat = read_cpc_cl_stat_conf();
|
||||
/*
|
||||
* If we're attempting to suspend the system and power down all
|
||||
* of the cores, the JTAG detect bit indicates that the CPC will
|
||||
* instead put the cores into clock-off state. In this state
|
||||
* a connected debugger can cause the CPU to attempt
|
||||
* interactions with the powered down system. At best this will
|
||||
* fail. At worst, it can hang the NoC, requiring a hard reset.
|
||||
* To avoid this, just block system suspend if a JTAG probe
|
||||
* is detected.
|
||||
*/
|
||||
if (stat & CPC_Cx_STAT_CONF_EJTAG_PROBE) {
|
||||
pr_warn("JTAG probe is connected - abort suspend\n");
|
||||
return NOTIFY_BAD;
|
||||
}
|
||||
return NOTIFY_DONE;
|
||||
default:
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
}
|
||||
|
||||
static int __init cps_pm_init(void)
|
||||
{
|
||||
/* A CM is required for all non-coherent states */
|
||||
|
|
@ -705,6 +734,8 @@ static int __init cps_pm_init(void)
|
|||
pr_warn("pm-cps: no CPC, clock & power gating unavailable\n");
|
||||
}
|
||||
|
||||
pm_notifier(cps_pm_power_notifier, 0);
|
||||
|
||||
return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "mips/cps_pm:online",
|
||||
cps_pm_online_cpu, NULL);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,6 +13,9 @@
|
|||
#include <linux/reboot.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <asm/compiler.h>
|
||||
#include <asm/idle.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/reboot.h>
|
||||
|
||||
/*
|
||||
|
|
@ -26,6 +29,62 @@ void (*pm_power_off)(void);
|
|||
|
||||
EXPORT_SYMBOL(pm_power_off);
|
||||
|
||||
static void machine_hang(void)
|
||||
{
|
||||
/*
|
||||
* We're hanging the system so we don't want to be interrupted anymore.
|
||||
* Any interrupt handlers that ran would at best be useless & at worst
|
||||
* go awry because the system isn't in a functional state.
|
||||
*/
|
||||
local_irq_disable();
|
||||
|
||||
/*
|
||||
* Mask all interrupts, giving us a better chance of remaining in the
|
||||
* low power wait state.
|
||||
*/
|
||||
clear_c0_status(ST0_IM);
|
||||
|
||||
while (true) {
|
||||
if (cpu_has_mips_r) {
|
||||
/*
|
||||
* We know that the wait instruction is supported so
|
||||
* make use of it directly, leaving interrupts
|
||||
* disabled.
|
||||
*/
|
||||
asm volatile(
|
||||
".set push\n\t"
|
||||
".set " MIPS_ISA_ARCH_LEVEL "\n\t"
|
||||
"wait\n\t"
|
||||
".set pop");
|
||||
} else if (cpu_wait) {
|
||||
/*
|
||||
* Try the cpu_wait() callback. This isn't ideal since
|
||||
* it'll re-enable interrupts, but that ought to be
|
||||
* harmless given that they're all masked.
|
||||
*/
|
||||
cpu_wait();
|
||||
local_irq_disable();
|
||||
} else {
|
||||
/*
|
||||
* We're going to burn some power running round the
|
||||
* loop, but we don't really have a choice. This isn't
|
||||
* a path we should expect to run for long during
|
||||
* typical use anyway.
|
||||
*/
|
||||
}
|
||||
|
||||
/*
|
||||
* In most modern MIPS CPUs interrupts will cause the wait
|
||||
* instruction to graduate even when disabled, and in some
|
||||
* cases even when masked. In order to prevent a timer
|
||||
* interrupt from continuously taking us out of the low power
|
||||
* wait state, we clear any pending timer interrupt here.
|
||||
*/
|
||||
if (cpu_has_counter)
|
||||
write_c0_compare(0);
|
||||
}
|
||||
}
|
||||
|
||||
void machine_restart(char *command)
|
||||
{
|
||||
if (_machine_restart)
|
||||
|
|
@ -38,8 +97,7 @@ void machine_restart(char *command)
|
|||
do_kernel_restart(command);
|
||||
mdelay(1000);
|
||||
pr_emerg("Reboot failed -- System halted\n");
|
||||
local_irq_disable();
|
||||
while (1);
|
||||
machine_hang();
|
||||
}
|
||||
|
||||
void machine_halt(void)
|
||||
|
|
@ -51,8 +109,7 @@ void machine_halt(void)
|
|||
preempt_disable();
|
||||
smp_send_stop();
|
||||
#endif
|
||||
local_irq_disable();
|
||||
while (1);
|
||||
machine_hang();
|
||||
}
|
||||
|
||||
void machine_power_off(void)
|
||||
|
|
@ -64,6 +121,5 @@ void machine_power_off(void)
|
|||
preempt_disable();
|
||||
smp_send_stop();
|
||||
#endif
|
||||
local_irq_disable();
|
||||
while (1);
|
||||
machine_hang();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -155,7 +155,8 @@ void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_add
|
|||
add_memory_region(start, size, BOOT_MEM_RAM);
|
||||
}
|
||||
|
||||
bool __init memory_region_available(phys_addr_t start, phys_addr_t size)
|
||||
static bool __init __maybe_unused memory_region_available(phys_addr_t start,
|
||||
phys_addr_t size)
|
||||
{
|
||||
int i;
|
||||
bool in_ram = false, free = true;
|
||||
|
|
@ -453,7 +454,7 @@ static void __init bootmem_init(void)
|
|||
pr_info("Wasting %lu bytes for tracking %lu unused pages\n",
|
||||
(min_low_pfn - ARCH_PFN_OFFSET) * sizeof(struct page),
|
||||
min_low_pfn - ARCH_PFN_OFFSET);
|
||||
} else if (min_low_pfn < ARCH_PFN_OFFSET) {
|
||||
} else if (ARCH_PFN_OFFSET - min_low_pfn > 0UL) {
|
||||
pr_info("%lu free pages won't be used\n",
|
||||
ARCH_PFN_OFFSET - min_low_pfn);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -30,7 +30,6 @@
|
|||
#include <linux/hardirq.h>
|
||||
#include <linux/gfp.h>
|
||||
#include <linux/kcore.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/initrd.h>
|
||||
|
||||
#include <asm/asm-offsets.h>
|
||||
|
|
@ -46,7 +45,6 @@
|
|||
#include <asm/pgalloc.h>
|
||||
#include <asm/tlb.h>
|
||||
#include <asm/fixmap.h>
|
||||
#include <asm/maar.h>
|
||||
|
||||
/*
|
||||
* We have up to 8 empty zeroed pages so we can map one of the right colour
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
*/
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/isa-rev.h>
|
||||
#include <asm/regdef.h>
|
||||
#include "bpf_jit.h"
|
||||
|
||||
|
|
@ -65,7 +66,7 @@ FEXPORT(sk_load_word_positive)
|
|||
lw $r_A, 0(t1)
|
||||
.set noreorder
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
|
||||
# if MIPS_ISA_REV >= 2
|
||||
wsbh t0, $r_A
|
||||
rotr $r_A, t0, 16
|
||||
# else
|
||||
|
|
@ -92,7 +93,7 @@ FEXPORT(sk_load_half_positive)
|
|||
PTR_ADDU t1, $r_skb_data, offset
|
||||
lhu $r_A, 0(t1)
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
|
||||
# if MIPS_ISA_REV >= 2
|
||||
wsbh $r_A, $r_A
|
||||
# else
|
||||
sll t0, $r_A, 8
|
||||
|
|
@ -170,7 +171,7 @@ FEXPORT(sk_load_byte_positive)
|
|||
NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp)
|
||||
bpf_slow_path_common(4)
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
|
||||
# if MIPS_ISA_REV >= 2
|
||||
wsbh t0, $r_s0
|
||||
jr $r_ra
|
||||
rotr $r_A, t0, 16
|
||||
|
|
@ -196,7 +197,7 @@ NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp)
|
|||
NESTED(bpf_slow_path_half, (6 * SZREG), $r_sp)
|
||||
bpf_slow_path_common(2)
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
|
||||
# if MIPS_ISA_REV >= 2
|
||||
jr $r_ra
|
||||
wsbh $r_A, $r_s0
|
||||
# else
|
||||
|
|
|
|||
|
|
@ -315,6 +315,7 @@ static int mt7620_pci_probe(struct platform_device *pdev)
|
|||
break;
|
||||
|
||||
case MT762X_SOC_MT7628AN:
|
||||
case MT762X_SOC_MT7688:
|
||||
if (mt7628_pci_hw_init(pdev))
|
||||
return -1;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -319,7 +319,7 @@ static void __init rbtx4927_mtd_init(void)
|
|||
|
||||
static void __init rbtx4927_gpioled_init(void)
|
||||
{
|
||||
static struct gpio_led leds[] = {
|
||||
static const struct gpio_led leds[] = {
|
||||
{ .name = "gpioled:green:0", .gpio = 0, .active_low = 1, },
|
||||
{ .name = "gpioled:green:1", .gpio = 1, .active_low = 1, },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,6 +10,8 @@
|
|||
|
||||
#include "vdso.h"
|
||||
|
||||
#include <asm/isa-rev.h>
|
||||
|
||||
#include <linux/elfnote.h>
|
||||
#include <linux/version.h>
|
||||
|
||||
|
|
@ -40,11 +42,7 @@ __mips_abiflags:
|
|||
.byte __mips /* isa_level */
|
||||
|
||||
/* isa_rev */
|
||||
#ifdef __mips_isa_rev
|
||||
.byte __mips_isa_rev
|
||||
#else
|
||||
.byte 0
|
||||
#endif
|
||||
.byte MIPS_ISA_REV
|
||||
|
||||
/* gpr_size */
|
||||
#ifdef __mips64
|
||||
|
|
@ -54,7 +52,7 @@ __mips_abiflags:
|
|||
#endif
|
||||
|
||||
/* cpr1_size */
|
||||
#if (defined(__mips_isa_rev) && __mips_isa_rev >= 6) || defined(__mips64)
|
||||
#if (MIPS_ISA_REV >= 6) || defined(__mips64)
|
||||
.byte 2 /* AFL_REG_64 */
|
||||
#else
|
||||
.byte 1 /* AFL_REG_32 */
|
||||
|
|
|
|||
|
|
@ -500,6 +500,15 @@ config CRYPTO_CRC32_PCLMUL
|
|||
which will enable any routine to use the CRC-32-IEEE 802.3 checksum
|
||||
and gain better performance as compared with the table implementation.
|
||||
|
||||
config CRYPTO_CRC32_MIPS
|
||||
tristate "CRC32c and CRC32 CRC algorithm (MIPS)"
|
||||
depends on MIPS_CRC_SUPPORT
|
||||
select CRYPTO_HASH
|
||||
help
|
||||
CRC32c and CRC32 CRC algorithms implemented using mips crypto
|
||||
instructions, when available.
|
||||
|
||||
|
||||
config CRYPTO_CRCT10DIF
|
||||
tristate "CRCT10DIF algorithm"
|
||||
select CRYPTO_HASH
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ config BCM47XX_NVRAM
|
|||
config BCM47XX_SPROM
|
||||
bool "Broadcom SPROM driver"
|
||||
depends on BCM47XX_NVRAM
|
||||
select GENERIC_NET_UTILS
|
||||
help
|
||||
Broadcom devices store configuration data in SPROM. Accessing it is
|
||||
specific to the bus host type, e.g. PCI(e) devices have it mapped in
|
||||
|
|
|
|||
|
|
@ -137,20 +137,6 @@ static void nvram_read_leddc(const char *prefix, const char *name,
|
|||
*leddc_off_time = (val >> 16) & 0xff;
|
||||
}
|
||||
|
||||
static void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
|
||||
{
|
||||
if (strchr(buf, ':'))
|
||||
sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
|
||||
&macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
|
||||
&macaddr[5]);
|
||||
else if (strchr(buf, '-'))
|
||||
sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0],
|
||||
&macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
|
||||
&macaddr[5]);
|
||||
else
|
||||
pr_warn("Can not parse mac address: %s\n", buf);
|
||||
}
|
||||
|
||||
static void nvram_read_macaddr(const char *prefix, const char *name,
|
||||
u8 val[6], bool fallback)
|
||||
{
|
||||
|
|
@ -161,7 +147,9 @@ static void nvram_read_macaddr(const char *prefix, const char *name,
|
|||
if (err < 0)
|
||||
return;
|
||||
|
||||
bcm47xx_nvram_parse_macaddr(buf, val);
|
||||
strreplace(buf, '-', ':');
|
||||
if (!mac_pton(buf, val))
|
||||
pr_warn("Can not parse mac address: %s\n", buf);
|
||||
}
|
||||
|
||||
static void nvram_read_alpha2(const char *prefix, const char *name,
|
||||
|
|
|
|||
Loading…
Reference in New Issue