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drm/i915/chv: Move data lane deassert to encoder pre_enable

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We need to pick the correct data lanes based on the port not the
pipe, so move the data lane deassert into the encoder .pre_enable()
hook from the chv_enable_pll().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2014-04-09 13:28:58 +03:00 committed by Daniel Vetter
parent a11b07039d
commit 949c1d43d6
3 changed files with 15 additions and 7 deletions
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5
drivers/gpu/drm/i915/intel_display.c
View file

@ -1603,11 +1603,6 @@ static void chv_enable_pll(struct intel_crtc *crtc)
I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
POSTING_READ(DPLL_MD(pipe));
/* Deassert soft data lane reset*/
tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
mutex_unlock(&dev_priv->dpio_lock);
}

9
drivers/gpu/drm/i915/intel_dp.c
View file

@ -1994,9 +1994,16 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
enum dpio_channel ch = vlv_dport_to_channel(dport);
int pipe = intel_crtc->pipe;
int data, i;
u32 val;
mutex_lock(&dev_priv->dpio_lock);
/* Deassert soft data lane reset*/
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
/* Program Tx lane latency optimal setting*/
mutex_lock(&dev_priv->dpio_lock);
for (i = 0; i < 4; i++) {
/* Set the latency optimal bit */
data = (i == 1) ? 0x0 : 0x6;

8
drivers/gpu/drm/i915/intel_hdmi.c
View file

@ -1257,8 +1257,14 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
int data, i;
u32 val;
/* Program Tx latency optimal setting */
mutex_lock(&dev_priv->dpio_lock);
/* Deassert soft data lane reset*/
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
/* Program Tx latency optimal setting */
for (i = 0; i < 4; i++) {
/* Set the latency optimal bit */
data = (i == 1) ? 0x0 : 0x6;