drm/i915/icl: add pll mapping for DSI
Add encoder specific pll mapping for DSI. The differences with the DDI version are big enough to warrant a separate function. v2: add posting read (Madhav) Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181203094326.28294-1-jani.nikula@intel.com
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@ -570,6 +570,28 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
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mutex_unlock(&dev_priv->dpll_lock);
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}
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static void gen11_dsi_map_pll(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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struct intel_shared_dpll *pll = crtc_state->shared_dpll;
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enum port port;
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u32 val;
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mutex_lock(&dev_priv->dpll_lock);
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val = I915_READ(DPCLKA_CFGCR0_ICL);
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for_each_dsi_port(port, intel_dsi->ports) {
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val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
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val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
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}
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I915_WRITE(DPCLKA_CFGCR0_ICL, val);
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POSTING_READ(DPCLKA_CFGCR0_ICL);
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mutex_unlock(&dev_priv->dpll_lock);
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}
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static void
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gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config)
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@ -978,6 +1000,9 @@ static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
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{
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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/* step3b */
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gen11_dsi_map_pll(encoder, pipe_config);
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/* step4: enable DSI port and DPHY */
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gen11_dsi_enable_port_and_phy(encoder, pipe_config);
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