drm/radeon/kms: setup mc chremap properly on r7xx/evergreen
Should improve performance slightly and possibly fix some issues. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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27641c3f00
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@ -1382,6 +1382,42 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
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return backend_map;
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}
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static void evergreen_program_channel_remap(struct radeon_device *rdev)
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{
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u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
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tmp = RREG32(MC_SHARED_CHMAP);
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switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
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case 0:
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case 1:
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case 2:
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case 3:
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default:
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/* default mapping */
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mc_shared_chremap = 0x00fac688;
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break;
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}
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switch (rdev->family) {
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case CHIP_HEMLOCK:
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case CHIP_CYPRESS:
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tcp_chan_steer_lo = 0x54763210;
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tcp_chan_steer_hi = 0x0000ba98;
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break;
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case CHIP_JUNIPER:
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case CHIP_REDWOOD:
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case CHIP_CEDAR:
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default:
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tcp_chan_steer_lo = 0x76543210;
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tcp_chan_steer_hi = 0x0000ba98;
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break;
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}
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WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
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WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
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WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
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}
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static void evergreen_gpu_init(struct radeon_device *rdev)
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{
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u32 cc_rb_backend_disable = 0;
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@ -1685,6 +1721,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
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WREG32(HDP_ADDR_CONFIG, gb_addr_config);
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evergreen_program_channel_remap(rdev);
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num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
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grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
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@ -180,6 +180,7 @@
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#define MC_SHARED_CHMAP 0x2004
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#define NOOFCHAN_SHIFT 12
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#define NOOFCHAN_MASK 0x00003000
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#define MC_SHARED_CHREMAP 0x2008
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#define MC_ARB_RAMCFG 0x2760
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#define NOOFBANK_SHIFT 0
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@ -348,6 +349,9 @@
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#define SYNC_WALKER (1 << 25)
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#define SYNC_ALIGNER (1 << 26)
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#define TCP_CHAN_STEER_LO 0x960c
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#define TCP_CHAN_STEER_HI 0x9610
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#define VGT_CACHE_INVALIDATION 0x88C4
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#define CACHE_INVALIDATION(x) ((x) << 0)
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#define VC_ONLY 0
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@ -489,6 +489,49 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
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return backend_map;
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}
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static void rv770_program_channel_remap(struct radeon_device *rdev)
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{
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u32 tcp_chan_steer, mc_shared_chremap, tmp;
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bool force_no_swizzle;
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switch (rdev->family) {
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case CHIP_RV770:
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case CHIP_RV730:
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force_no_swizzle = false;
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break;
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case CHIP_RV710:
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case CHIP_RV740:
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default:
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force_no_swizzle = true;
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break;
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}
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tmp = RREG32(MC_SHARED_CHMAP);
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switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
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case 0:
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case 1:
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default:
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/* default mapping */
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mc_shared_chremap = 0x00fac688;
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break;
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case 2:
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case 3:
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if (force_no_swizzle)
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mc_shared_chremap = 0x00fac688;
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else
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mc_shared_chremap = 0x00bbc298;
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break;
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}
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if (rdev->family == CHIP_RV740)
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tcp_chan_steer = 0x00ef2a60;
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else
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tcp_chan_steer = 0x00fac688;
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WREG32(TCP_CHAN_STEER, tcp_chan_steer);
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WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
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}
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static void rv770_gpu_init(struct radeon_device *rdev)
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{
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int i, j, num_qd_pipes;
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@ -688,6 +731,8 @@ static void rv770_gpu_init(struct radeon_device *rdev)
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WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
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WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
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rv770_program_channel_remap(rdev);
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WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
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WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
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WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
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@ -138,6 +138,7 @@
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#define MC_SHARED_CHMAP 0x2004
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#define NOOFCHAN_SHIFT 12
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#define NOOFCHAN_MASK 0x00003000
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#define MC_SHARED_CHREMAP 0x2008
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#define MC_ARB_RAMCFG 0x2760
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#define NOOFBANK_SHIFT 0
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@ -303,6 +304,7 @@
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#define BILINEAR_PRECISION_8_BIT (1 << 31)
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#define TCP_CNTL 0x9610
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#define TCP_CHAN_STEER 0x9614
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#define VGT_CACHE_INVALIDATION 0x88C4
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#define CACHE_INVALIDATION(x) ((x)<<0)
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