EDAC, ie31200_edac: Add Skylake support
Skylake adjusts some register locations, but otherwise follows the existing model quite closely. I was able to verify that the 'ce_count' increments when 'bad dimms' are used. The accounting of 'ce_count' and 'ue_count' is the primary functionality of interest for us. Tested on Intel(R) Xeon(R) CPU E3-1260L v5 @ 2.90GHz. Signed-off-by: Jason Baron <jbaron@akamai.com> Acked-by: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1462547927-22679-1-git-send-email-jbaron@akamai.com Signed-off-by: Borislav Petkov <bp@suse.de>hifive-unleashed-5.1
Jason Baron
Borislav Petkov
parent
2c1ea4c700
commit
953dee9bbd
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@ -17,6 +17,7 @@
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* 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
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* 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
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* 0c08: Xeon E3-1200 v3 Processor DRAM Controller
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* 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
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*
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* Based on Intel specification:
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* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
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@ -55,6 +56,7 @@
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
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#define IE31200_DIMMS 4
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#define IE31200_RANKS 8
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@ -105,8 +107,11 @@
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* 1 Multiple Bit Error Status (MERRSTS)
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* 0 Correctable Error Status (CERRSTS)
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*/
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#define IE31200_C0ECCERRLOG 0x40c8
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#define IE31200_C1ECCERRLOG 0x44c8
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#define IE31200_C0ECCERRLOG_SKL 0x4048
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#define IE31200_C1ECCERRLOG_SKL 0x4448
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#define IE31200_ECCERRLOG_CE BIT(0)
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#define IE31200_ECCERRLOG_UE BIT(1)
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#define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27)
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@ -123,17 +128,28 @@
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#define IE31200_CAPID0_DDPCD BIT(6)
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#define IE31200_CAPID0_ECC BIT(1)
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#define IE31200_MAD_DIMM_0_OFFSET 0x5004
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#define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0)
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#define IE31200_MAD_DIMM_A_RANK BIT(17)
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#define IE31200_MAD_DIMM_A_WIDTH BIT(19)
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#define IE31200_MAD_DIMM_0_OFFSET 0x5004
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#define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C
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#define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0)
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#define IE31200_MAD_DIMM_A_RANK BIT(17)
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#define IE31200_MAD_DIMM_A_RANK_SHIFT 17
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#define IE31200_MAD_DIMM_A_RANK_SKL BIT(10)
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#define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10
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#define IE31200_MAD_DIMM_A_WIDTH BIT(19)
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#define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19
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#define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8)
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#define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8
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#define IE31200_PAGES(n) (n << (28 - PAGE_SHIFT))
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/* Skylake reports 1GB increments, everything else is 256MB */
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#define IE31200_PAGES(n, skl) \
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(n << (28 + (2 * skl) - PAGE_SHIFT))
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static int nr_channels;
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struct ie31200_priv {
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void __iomem *window;
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void __iomem *c0errlog;
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void __iomem *c1errlog;
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};
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enum ie31200_chips {
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@ -157,9 +173,9 @@ static const struct ie31200_dev_info ie31200_devs[] = {
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};
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struct dimm_data {
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u8 size; /* in 256MB multiples */
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u8 size; /* in multiples of 256MB, except Skylake is 1GB */
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u8 dual_rank : 1,
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x16_width : 1; /* 0 means x8 width */
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x16_width : 2; /* 0 means x8 width */
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};
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static int how_many_channels(struct pci_dev *pdev)
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@ -197,11 +213,10 @@ static bool ecc_capable(struct pci_dev *pdev)
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return true;
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}
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static int eccerrlog_row(int channel, u64 log)
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static int eccerrlog_row(u64 log)
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{
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int rank = ((log & IE31200_ECCERRLOG_RANK_BITS) >>
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IE31200_ECCERRLOG_RANK_SHIFT);
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return rank | (channel * IE31200_RANKS_PER_CHANNEL);
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return ((log & IE31200_ECCERRLOG_RANK_BITS) >>
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IE31200_ECCERRLOG_RANK_SHIFT);
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}
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static void ie31200_clear_error_info(struct mem_ctl_info *mci)
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@ -219,7 +234,6 @@ static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
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{
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struct pci_dev *pdev;
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struct ie31200_priv *priv = mci->pvt_info;
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void __iomem *window = priv->window;
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pdev = to_pci_dev(mci->pdev);
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@ -232,9 +246,9 @@ static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
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if (!(info->errsts & IE31200_ERRSTS_BITS))
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return;
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info->eccerrlog[0] = lo_hi_readq(window + IE31200_C0ECCERRLOG);
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info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
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if (nr_channels == 2)
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info->eccerrlog[1] = lo_hi_readq(window + IE31200_C1ECCERRLOG);
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info->eccerrlog[1] = lo_hi_readq(priv->c1errlog);
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pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);
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@ -245,10 +259,10 @@ static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
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* should be UE info.
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*/
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if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
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info->eccerrlog[0] = lo_hi_readq(window + IE31200_C0ECCERRLOG);
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info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
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if (nr_channels == 2)
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info->eccerrlog[1] =
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lo_hi_readq(window + IE31200_C1ECCERRLOG);
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lo_hi_readq(priv->c1errlog);
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}
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ie31200_clear_error_info(mci);
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@ -274,14 +288,14 @@ static void ie31200_process_error_info(struct mem_ctl_info *mci,
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if (log & IE31200_ECCERRLOG_UE) {
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
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0, 0, 0,
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eccerrlog_row(channel, log),
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eccerrlog_row(log),
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channel, -1,
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"ie31200 UE", "");
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} else if (log & IE31200_ECCERRLOG_CE) {
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
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0, 0,
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IE31200_ECCERRLOG_SYNDROME(log),
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eccerrlog_row(channel, log),
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eccerrlog_row(log),
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channel, -1,
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"ie31200 CE", "");
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}
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@ -326,6 +340,33 @@ static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev)
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return window;
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}
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static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
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int chan)
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{
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dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE;
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dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0;
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dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >>
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(IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4)));
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}
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static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
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int chan)
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{
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dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE;
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dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0;
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dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0;
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}
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static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan,
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bool skl)
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{
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if (skl)
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__skl_populate_dimm_info(dd, addr_decode, chan);
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else
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__populate_dimm_info(dd, addr_decode, chan);
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}
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static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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{
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int i, j, ret;
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@ -334,7 +375,8 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
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void __iomem *window;
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struct ie31200_priv *priv;
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u32 addr_decode;
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u32 addr_decode, mad_offset;
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bool skl = (pdev->device == PCI_DEVICE_ID_INTEL_IE31200_HB_8);
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edac_dbg(0, "MC:\n");
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@ -363,7 +405,10 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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edac_dbg(3, "MC: init mci\n");
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mci->pdev = &pdev->dev;
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mci->mtype_cap = MEM_FLAG_DDR3;
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if (skl)
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mci->mtype_cap = MEM_FLAG_DDR4;
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else
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mci->mtype_cap = MEM_FLAG_DDR3;
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mci->edac_ctl_cap = EDAC_FLAG_SECDED;
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mci->edac_cap = EDAC_FLAG_SECDED;
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mci->mod_name = EDAC_MOD_STR;
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@ -374,19 +419,24 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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mci->ctl_page_to_phys = NULL;
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priv = mci->pvt_info;
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priv->window = window;
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if (skl) {
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priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL;
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priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL;
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mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL;
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} else {
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priv->c0errlog = window + IE31200_C0ECCERRLOG;
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priv->c1errlog = window + IE31200_C1ECCERRLOG;
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mad_offset = IE31200_MAD_DIMM_0_OFFSET;
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}
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/* populate DIMM info */
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for (i = 0; i < IE31200_CHANNELS; i++) {
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addr_decode = readl(window + IE31200_MAD_DIMM_0_OFFSET +
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addr_decode = readl(window + mad_offset +
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(i * 4));
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edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);
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for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {
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dimm_info[i][j].size = (addr_decode >> (j * 8)) &
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IE31200_MAD_DIMM_SIZE;
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dimm_info[i][j].dual_rank = (addr_decode &
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(IE31200_MAD_DIMM_A_RANK << j)) ? 1 : 0;
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dimm_info[i][j].x16_width = (addr_decode &
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(IE31200_MAD_DIMM_A_WIDTH << j)) ? 1 : 0;
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populate_dimm_info(&dimm_info[i][j], addr_decode, j,
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skl);
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edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",
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dimm_info[i][j].size,
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dimm_info[i][j].dual_rank,
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@ -405,7 +455,7 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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struct dimm_info *dimm;
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unsigned long nr_pages;
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nr_pages = IE31200_PAGES(dimm_info[j][i].size);
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nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl);
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if (nr_pages == 0)
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continue;
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@ -417,7 +467,10 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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dimm->nr_pages = nr_pages;
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edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
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dimm->grain = 8; /* just a guess */
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dimm->mtype = MEM_DDR3;
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if (skl)
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dimm->mtype = MEM_DDR4;
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else
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dimm->mtype = MEM_DDR3;
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dimm->dtype = DEV_UNKNOWN;
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dimm->edac_mode = EDAC_UNKNOWN;
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}
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@ -426,7 +479,10 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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dimm->nr_pages = nr_pages;
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edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
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dimm->grain = 8; /* same guess */
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dimm->mtype = MEM_DDR3;
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if (skl)
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dimm->mtype = MEM_DDR4;
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else
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dimm->mtype = MEM_DDR3;
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dimm->dtype = DEV_UNKNOWN;
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dimm->edac_mode = EDAC_UNKNOWN;
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}
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@ -500,6 +556,9 @@ static const struct pci_device_id ie31200_pci_tbl[] = {
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{
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PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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IE31200},
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{
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PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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IE31200},
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{
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0,
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} /* 0 terminated list. */
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