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drm/rockchip: vop: move write_relaxed flags to vop register

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Since the drm atomic framework, only a small part of the vop
register needs sync write, Currently seems only following registers
need sync write:
   cfg_done, standby and interrupt related register.

All ctrl registers are using the sync write method that is
inefficient, hardcode the write_relaxed flags to vop registers,
then can only do synchronize write for those actual needed register.

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1501049953-5946-1-git-send-email-mark.yao@rock-chips.com
This commit is contained in:
Mark yao 2017-07-26 14:19:12 +08:00 committed by Mark Yao
parent 60b7ae7fa2
commit 9548e1b49a
3 changed files with 36 additions and 35 deletions
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28
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View file

@ -42,33 +42,27 @@
#include "rockchip_drm_psr.h" #include "rockchip_drm_psr.h"
#include "rockchip_drm_vop.h" #include "rockchip_drm_vop.h"
#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ #define REG_SET(x, base, reg, v) \
vop_mask_write(x, off, mask, shift, v, write_mask, true) vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \
v, reg.write_mask, reg.relaxed)
#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ #define REG_SET_MASK(x, base, reg, mask, v) \
vop_mask_write(x, off, mask, shift, v, write_mask, false) vop_mask_write(x, base + reg.offset, \
mask, reg.shift, v, reg.write_mask, reg.relaxed)
#define REG_SET(x, base, reg, v, mode) \
__REG_SET_##mode(x, base + reg.offset, \
reg.mask, reg.shift, v, reg.write_mask)
#define REG_SET_MASK(x, base, reg, mask, v, mode) \
__REG_SET_##mode(x, base + reg.offset, \
mask, reg.shift, v, reg.write_mask)
#define VOP_WIN_SET(x, win, name, v) \ #define VOP_WIN_SET(x, win, name, v) \
REG_SET(x, win->base, win->phy->name, v, RELAXED) REG_SET(x, win->base, win->phy->name, v)
#define VOP_SCL_SET(x, win, name, v) \ #define VOP_SCL_SET(x, win, name, v) \
REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) REG_SET(x, win->base, win->phy->scl->name, v)
#define VOP_SCL_SET_EXT(x, win, name, v) \ #define VOP_SCL_SET_EXT(x, win, name, v) \
REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) REG_SET(x, win->base, win->phy->scl->ext->name, v)
#define VOP_CTRL_SET(x, name, v) \ #define VOP_CTRL_SET(x, name, v) \
REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) REG_SET(x, 0, (x)->data->ctrl->name, v)
#define VOP_INTR_GET(vop, name) \ #define VOP_INTR_GET(vop, name) \
vop_read_reg(vop, 0, &vop->data->ctrl->name) vop_read_reg(vop, 0, &vop->data->ctrl->name)
#define VOP_INTR_SET(vop, name, mask, v) \ #define VOP_INTR_SET(vop, name, mask, v) \
REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v)
#define VOP_INTR_SET_TYPE(vop, name, type, v) \ #define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \ do { \
int i, reg = 0, mask = 0; \ int i, reg = 0, mask = 0; \

1
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View file

@ -29,6 +29,7 @@ struct vop_reg {
uint32_t shift; uint32_t shift;
uint32_t mask; uint32_t mask;
bool write_mask; bool write_mask;
bool relaxed;
}; };
struct vop_ctrl { struct vop_ctrl {

42
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View file

@ -20,17 +20,23 @@
#include "rockchip_drm_vop.h" #include "rockchip_drm_vop.h"
#include "rockchip_vop_reg.h" #include "rockchip_vop_reg.h"
#define VOP_REG(off, _mask, s) \ #define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \
{.offset = off, \ { \
.offset = off, \
.mask = _mask, \ .mask = _mask, \
.shift = s, \ .shift = _shift, \
.write_mask = false,} .write_mask = _write_mask, \
.relaxed = _relaxed, \
}
#define VOP_REG_MASK(off, _mask, s) \ #define VOP_REG(off, _mask, _shift) \
{.offset = off, \ _VOP_REG(off, _mask, _shift, false, true)
.mask = _mask, \
.shift = s, \ #define VOP_REG_SYNC(off, _mask, _shift) \
.write_mask = true,} _VOP_REG(off, _mask, _shift, false, false)
#define VOP_REG_MASK_SYNC(off, _mask, _shift) \
_VOP_REG(off, _mask, _shift, true, false)
static const uint32_t formats_win_full[] = { static const uint32_t formats_win_full[] = {
DRM_FORMAT_XRGB8888, DRM_FORMAT_XRGB8888,
@ -116,7 +122,7 @@ static const struct vop_intr rk3036_intr = {
}; };
static const struct vop_ctrl rk3036_ctrl_data = { static const struct vop_ctrl rk3036_ctrl_data = {
.standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30),
.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
.dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
@ -125,7 +131,7 @@ static const struct vop_ctrl rk3036_ctrl_data = {
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
.line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
}; };
static const struct vop_data rk3036_vop = { static const struct vop_data rk3036_vop = {
@ -201,7 +207,7 @@ static const struct vop_win_phy rk3288_win23_data = {
}; };
static const struct vop_ctrl rk3288_ctrl_data = { static const struct vop_ctrl rk3288_ctrl_data = {
.standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22), .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22),
.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20), .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
@ -222,7 +228,7 @@ static const struct vop_ctrl rk3288_ctrl_data = {
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
.line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
.global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11), .global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11),
.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
}; };
/* /*
@ -266,7 +272,7 @@ static const struct vop_data rk3288_vop = {
}; };
static const struct vop_ctrl rk3399_ctrl_data = { static const struct vop_ctrl rk3399_ctrl_data = {
.standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22), .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22),
.gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
.dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
.rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12), .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
@ -290,7 +296,7 @@ static const struct vop_ctrl rk3399_ctrl_data = {
.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0), .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
.line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0), .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0),
.line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16), .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16),
.cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0), .cfg_done = VOP_REG_MASK_SYNC(RK3399_REG_CFG_DONE, 0x1, 0),
}; };
static const int rk3399_vop_intrs[] = { static const int rk3399_vop_intrs[] = {
@ -306,9 +312,9 @@ static const int rk3399_vop_intrs[] = {
static const struct vop_intr rk3399_vop_intr = { static const struct vop_intr rk3399_vop_intr = {
.intrs = rk3399_vop_intrs, .intrs = rk3399_vop_intrs,
.nintrs = ARRAY_SIZE(rk3399_vop_intrs), .nintrs = ARRAY_SIZE(rk3399_vop_intrs),
.status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0), .status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0xffff, 0),
.enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0), .enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0xffff, 0),
.clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0), .clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0xffff, 0),
}; };
static const struct vop_data rk3399_vop_big = { static const struct vop_data rk3399_vop_big = {