Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal into thermal-soc-fixes
Zhang Rui
commit
9550b8d1dc
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@ -6,16 +6,35 @@
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"samsung,exynos4412-tmu"
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"samsung,exynos4210-tmu"
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"samsung,exynos5250-tmu"
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"samsung,exynos5260-tmu"
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"samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
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"samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
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Exynos5420 (Must pass triminfo base and triminfo clock)
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"samsung,exynos5440-tmu"
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- interrupt-parent : The phandle for the interrupt controller
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- reg : Address range of the thermal registers. For soc's which has multiple
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instances of TMU and some registers are shared across all TMU's like
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interrupt related then 2 set of register has to supplied. First set
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belongs to each instance of TMU and second set belongs to common TMU
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registers.
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belongs to register set of TMU instance and second set belongs to
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registers shared with the TMU instance.
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NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
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channels 2, 3 and 4
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Use "samsung,exynos5420-tmu-ext-triminfo" in cases, there is a misplaced
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register, also provide clock to access that base.
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TRIMINFO at 0x1006c000 contains data for TMU channel 3
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TRIMINFO at 0x100a0000 contains data for TMU channel 4
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TRIMINFO at 0x10068000 contains data for TMU channel 2
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- interrupts : Should contain interrupt for thermal system
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- clocks : The main clock for TMU device
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- clocks : The main clocks for TMU device
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-- 1. operational clock for TMU channel
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-- 2. optional clock to access the shared registers of TMU channel
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- clock-names : Thermal system clock name
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-- "tmu_apbif" operational clock for current TMU channel
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-- "tmu_triminfo_apbif" clock to access the shared triminfo register
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for current TMU channel
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- vtmu-supply: This entry is optional and provides the regulator node supplying
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voltage to TMU. If needed this entry can be placed inside
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board/platform specific dts file.
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@ -43,6 +62,31 @@ Example 2):
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clock-names = "tmu_apbif";
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};
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Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
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tmu_cpu2: tmu@10068000 {
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compatible = "samsung,exynos5420-tmu-ext-triminfo";
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reg = <0x10068000 0x100>, <0x1006c000 0x4>;
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interrupts = <0 184 0>;
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clocks = <&clock 318>, <&clock 318>;
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clock-names = "tmu_apbif", "tmu_triminfo_apbif";
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};
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tmu_cpu3: tmu@1006c000 {
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compatible = "samsung,exynos5420-tmu-ext-triminfo";
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reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
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interrupts = <0 185 0>;
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clocks = <&clock 318>, <&clock 319>;
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clock-names = "tmu_apbif", "tmu_triminfo_apbif";
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};
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tmu_gpu: tmu@100a0000 {
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compatible = "samsung,exynos5420-tmu-ext-triminfo";
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reg = <0x100a0000 0x100>, <0x10068000 0x4>;
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interrupts = <0 215 0>;
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clocks = <&clock 319>, <&clock 318>;
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clock-names = "tmu_apbif", "tmu_triminfo_apbif";
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};
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Note: For multi-instance tmu each instance should have an alias correctly
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numbered in "aliases" node.
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@ -227,7 +227,7 @@ source "drivers/thermal/ti-soc-thermal/Kconfig"
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endmenu
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menu "Samsung thermal drivers"
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depends on PLAT_SAMSUNG
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depends on ARCH_EXYNOS
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source "drivers/thermal/samsung/Kconfig"
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endmenu
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@ -41,12 +41,13 @@
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* @id: identifier of the one instance of the TMU controller.
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* @pdata: pointer to the tmu platform/configuration data
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* @base: base address of the single instance of the TMU controller.
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* @base_common: base address of the common registers of the TMU controller.
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* @base_second: base address of the common registers of the TMU controller.
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* @irq: irq number of the TMU controller.
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* @soc: id of the SOC type.
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* @irq_work: pointer to the irq work structure.
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* @lock: lock to implement synchronization.
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* @clk: pointer to the clock structure.
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* @clk_sec: pointer to the clock structure for accessing the base_second.
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* @temp_error1: fused value of the first point trim.
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* @temp_error2: fused value of the second point trim.
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* @regulator: pointer to the TMU regulator structure.
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@ -56,12 +57,12 @@ struct exynos_tmu_data {
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int id;
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struct exynos_tmu_platform_data *pdata;
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void __iomem *base;
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void __iomem *base_common;
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void __iomem *base_second;
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int irq;
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enum soc_type soc;
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struct work_struct irq_work;
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struct mutex lock;
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struct clk *clk;
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struct clk *clk, *clk_sec;
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u8 temp_error1, temp_error2;
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struct regulator *regulator;
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struct thermal_sensor_conf *reg_conf;
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@ -152,6 +153,8 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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mutex_lock(&data->lock);
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clk_enable(data->clk);
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if (!IS_ERR(data->clk_sec))
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clk_enable(data->clk_sec);
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if (TMU_SUPPORTS(pdata, READY_STATUS)) {
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status = readb(data->base + reg->tmu_status);
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@ -186,7 +189,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
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}
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} else {
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trim_info = readl(data->base + reg->triminfo_data);
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/* On exynos5420 the triminfo register is in the shared space */
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if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
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trim_info = readl(data->base_second +
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reg->triminfo_data);
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else
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trim_info = readl(data->base + reg->triminfo_data);
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}
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data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
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data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
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@ -238,7 +246,7 @@ skip_calib_data:
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writeb(pdata->trigger_levels[i], data->base +
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reg->threshold_th0 + i * sizeof(reg->threshold_th0));
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writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
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writel(reg->intclr_rise_mask, data->base + reg->tmu_intclear);
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} else {
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/* Write temperature code for rising and falling threshold */
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for (i = 0;
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@ -265,8 +273,8 @@ skip_calib_data:
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writel(falling_threshold,
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data->base + reg->threshold_th1);
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writel((reg->inten_rise_mask << reg->inten_rise_shift) |
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(reg->inten_fall_mask << reg->inten_fall_shift),
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writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |
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(reg->intclr_fall_mask << reg->intclr_fall_shift),
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data->base + reg->tmu_intclear);
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/* if last threshold limit is also present */
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@ -298,10 +306,12 @@ skip_calib_data:
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}
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/*Clear the PMIN in the common TMU register*/
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if (reg->tmu_pmin && !data->id)
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writel(0, data->base_common + reg->tmu_pmin);
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writel(0, data->base_second + reg->tmu_pmin);
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out:
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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if (!IS_ERR(data->clk_sec))
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clk_disable(data->clk_sec);
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return ret;
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}
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@ -453,12 +463,16 @@ static void exynos_tmu_work(struct work_struct *work)
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const struct exynos_tmu_registers *reg = pdata->registers;
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unsigned int val_irq, val_type;
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if (!IS_ERR(data->clk_sec))
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clk_enable(data->clk_sec);
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/* Find which sensor generated this interrupt */
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if (reg->tmu_irqstatus) {
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val_type = readl(data->base_common + reg->tmu_irqstatus);
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val_type = readl(data->base_second + reg->tmu_irqstatus);
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if (!((val_type >> data->id) & 0x1))
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goto out;
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}
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if (!IS_ERR(data->clk_sec))
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clk_disable(data->clk_sec);
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exynos_report_trigger(data->reg_conf);
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mutex_lock(&data->lock);
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@ -498,6 +512,18 @@ static const struct of_device_id exynos_tmu_match[] = {
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.compatible = "samsung,exynos5250-tmu",
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.data = (void *)EXYNOS5250_TMU_DRV_DATA,
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},
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{
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.compatible = "samsung,exynos5260-tmu",
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.data = (void *)EXYNOS5260_TMU_DRV_DATA,
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},
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{
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.compatible = "samsung,exynos5420-tmu",
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.data = (void *)EXYNOS5420_TMU_DRV_DATA,
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},
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{
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.compatible = "samsung,exynos5420-tmu-ext-triminfo",
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.data = (void *)EXYNOS5420_TMU_DRV_DATA,
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},
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{
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.compatible = "samsung,exynos5440-tmu",
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.data = (void *)EXYNOS5440_TMU_DRV_DATA,
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@ -580,7 +606,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
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* Check if the TMU shares some registers and then try to map the
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* memory of common registers.
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*/
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if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
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if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
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return 0;
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if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
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@ -588,9 +614,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
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return -ENODEV;
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}
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data->base_common = devm_ioremap(&pdev->dev, res.start,
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data->base_second = devm_ioremap(&pdev->dev, res.start,
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resource_size(&res));
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if (!data->base_common) {
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if (!data->base_second) {
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dev_err(&pdev->dev, "Failed to ioremap memory\n");
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return -ENOMEM;
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}
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@ -629,13 +655,31 @@ static int exynos_tmu_probe(struct platform_device *pdev)
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return PTR_ERR(data->clk);
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}
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data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
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if (IS_ERR(data->clk_sec)) {
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if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
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dev_err(&pdev->dev, "Failed to get triminfo clock\n");
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return PTR_ERR(data->clk_sec);
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}
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} else {
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ret = clk_prepare(data->clk_sec);
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if (ret) {
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dev_err(&pdev->dev, "Failed to get clock\n");
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return ret;
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}
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}
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ret = clk_prepare(data->clk);
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if (ret)
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return ret;
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if (ret) {
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dev_err(&pdev->dev, "Failed to get clock\n");
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goto err_clk_sec;
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}
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if (pdata->type == SOC_ARCH_EXYNOS4210 ||
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pdata->type == SOC_ARCH_EXYNOS4412 ||
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pdata->type == SOC_ARCH_EXYNOS5250 ||
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pdata->type == SOC_ARCH_EXYNOS5260 ||
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pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
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pdata->type == SOC_ARCH_EXYNOS5440)
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data->soc = pdata->type;
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else {
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@ -704,6 +748,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
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return 0;
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err_clk:
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clk_unprepare(data->clk);
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err_clk_sec:
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if (!IS_ERR(data->clk_sec))
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clk_unprepare(data->clk_sec);
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return ret;
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}
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@ -716,6 +763,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
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exynos_unregister_thermal(data->reg_conf);
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clk_unprepare(data->clk);
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if (!IS_ERR(data->clk_sec))
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clk_unprepare(data->clk_sec);
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if (!IS_ERR(data->regulator))
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regulator_disable(data->regulator);
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@ -43,6 +43,8 @@ enum soc_type {
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SOC_ARCH_EXYNOS4210 = 1,
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SOC_ARCH_EXYNOS4412,
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SOC_ARCH_EXYNOS5250,
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SOC_ARCH_EXYNOS5260,
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SOC_ARCH_EXYNOS5420_TRIMINFO,
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SOC_ARCH_EXYNOS5440,
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};
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@ -60,7 +62,7 @@ enum soc_type {
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* state(active/idle) can be checked.
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* TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
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* sample time.
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* TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
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* TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
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* sensors shares some common registers.
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* TMU_SUPPORT - macro to compare the above features with the supplied.
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*/
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@ -70,7 +72,7 @@ enum soc_type {
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#define TMU_SUPPORT_FALLING_TRIP BIT(3)
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#define TMU_SUPPORT_READY_STATUS BIT(4)
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#define TMU_SUPPORT_EMUL_TIME BIT(5)
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#define TMU_SUPPORT_SHARED_MEMORY BIT(6)
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#define TMU_SUPPORT_ADDRESS_MULTIPLE BIT(6)
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#define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b)
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@ -122,10 +124,6 @@ enum soc_type {
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* @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
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* @tmu_inten: register containing the different threshold interrupt
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enable bits.
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* @inten_rise_shift: shift bits of all rising interrupt bits.
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* @inten_rise_mask: mask bits of all rising interrupt bits.
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* @inten_fall_shift: shift bits of all rising interrupt bits.
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* @inten_fall_mask: mask bits of all rising interrupt bits.
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* @inten_rise0_shift: shift bits of rising 0 interrupt bits.
|
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* @inten_rise1_shift: shift bits of rising 1 interrupt bits.
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* @inten_rise2_shift: shift bits of rising 2 interrupt bits.
|
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|
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@ -136,6 +134,10 @@ enum soc_type {
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* @inten_fall3_shift: shift bits of falling 3 interrupt bits.
|
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* @tmu_intstat: Register containing the interrupt status values.
|
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* @tmu_intclear: Register for clearing the raised interrupt status.
|
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* @intclr_fall_shift: shift bits for interrupt clear fall 0
|
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* @intclr_rise_shift: shift bits of all rising interrupt bits.
|
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* @intclr_rise_mask: mask bits of all rising interrupt bits.
|
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* @intclr_fall_mask: mask bits of all rising interrupt bits.
|
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* @emul_con: TMU emulation controller register.
|
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* @emul_temp_shift: shift bits of emulation temperature.
|
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* @emul_time_shift: shift bits of emulation time.
|
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|
|
@ -149,6 +151,7 @@ struct exynos_tmu_registers {
|
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u32 triminfo_85_shift;
|
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|
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u32 triminfo_ctrl;
|
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u32 triminfo_ctrl1;
|
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u32 triminfo_reload_shift;
|
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|
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u32 tmu_ctrl;
|
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|
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@ -191,10 +194,6 @@ struct exynos_tmu_registers {
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u32 threshold_th3_l0_shift;
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|
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u32 tmu_inten;
|
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u32 inten_rise_shift;
|
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u32 inten_rise_mask;
|
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u32 inten_fall_shift;
|
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u32 inten_fall_mask;
|
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u32 inten_rise0_shift;
|
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u32 inten_rise1_shift;
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u32 inten_rise2_shift;
|
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|
|
@ -207,6 +206,10 @@ struct exynos_tmu_registers {
|
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u32 tmu_intstat;
|
||||
|
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u32 tmu_intclear;
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u32 intclr_fall_shift;
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u32 intclr_rise_shift;
|
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u32 intclr_fall_mask;
|
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u32 intclr_rise_mask;
|
||||
|
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u32 emul_con;
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u32 emul_temp_shift;
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||||
|
|
|
|||
|
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@ -40,13 +40,13 @@ static const struct exynos_tmu_registers exynos4210_tmu_registers = {
|
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.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
|
||||
.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
|
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
|
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.inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
|
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
|
||||
.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
|
||||
.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
|
||||
.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
|
||||
.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
|
||||
.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
|
||||
.intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
|
||||
};
|
||||
|
||||
struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
|
||||
|
|
@ -112,10 +112,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
|
|||
.threshold_th0 = EXYNOS_THD_TEMP_RISE,
|
||||
.threshold_th1 = EXYNOS_THD_TEMP_FALL,
|
||||
.tmu_inten = EXYNOS_TMU_REG_INTEN,
|
||||
.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
|
||||
.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
|
||||
.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
|
||||
.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
|
||||
.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
|
||||
.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
|
||||
.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
|
||||
|
|
@ -123,6 +119,10 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
|
|||
.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
|
||||
.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
|
||||
.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
|
||||
.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
|
||||
.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
|
||||
.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
|
||||
.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
|
||||
.emul_con = EXYNOS_EMUL_CON,
|
||||
.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
|
||||
.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
|
||||
|
|
@ -194,6 +194,197 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5260)
|
||||
static const struct exynos_tmu_registers exynos5260_tmu_registers = {
|
||||
.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
|
||||
.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
|
||||
.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
|
||||
.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
|
||||
.tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
|
||||
.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
|
||||
.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
|
||||
.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
|
||||
.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
|
||||
.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
|
||||
.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
|
||||
.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
|
||||
.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
|
||||
.tmu_status = EXYNOS_TMU_REG_STATUS,
|
||||
.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
|
||||
.threshold_th0 = EXYNOS_THD_TEMP_RISE,
|
||||
.threshold_th1 = EXYNOS_THD_TEMP_FALL,
|
||||
.tmu_inten = EXYNOS5260_TMU_REG_INTEN,
|
||||
.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
|
||||
.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
|
||||
.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
|
||||
.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
|
||||
.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
|
||||
.tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
|
||||
.tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
|
||||
.intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
|
||||
.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
|
||||
.intclr_rise_mask = EXYNOS5260_TMU_RISE_INT_MASK,
|
||||
.intclr_fall_mask = EXYNOS5260_TMU_FALL_INT_MASK,
|
||||
.emul_con = EXYNOS5260_EMUL_CON,
|
||||
.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
|
||||
.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
|
||||
.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
|
||||
};
|
||||
|
||||
#define __EXYNOS5260_TMU_DATA \
|
||||
.threshold_falling = 10, \
|
||||
.trigger_levels[0] = 85, \
|
||||
.trigger_levels[1] = 103, \
|
||||
.trigger_levels[2] = 110, \
|
||||
.trigger_levels[3] = 120, \
|
||||
.trigger_enable[0] = true, \
|
||||
.trigger_enable[1] = true, \
|
||||
.trigger_enable[2] = true, \
|
||||
.trigger_enable[3] = false, \
|
||||
.trigger_type[0] = THROTTLE_ACTIVE, \
|
||||
.trigger_type[1] = THROTTLE_ACTIVE, \
|
||||
.trigger_type[2] = SW_TRIP, \
|
||||
.trigger_type[3] = HW_TRIP, \
|
||||
.max_trigger_level = 4, \
|
||||
.gain = 8, \
|
||||
.reference_voltage = 16, \
|
||||
.noise_cancel_mode = 4, \
|
||||
.cal_type = TYPE_ONE_POINT_TRIMMING, \
|
||||
.efuse_value = 55, \
|
||||
.min_efuse_value = 40, \
|
||||
.max_efuse_value = 100, \
|
||||
.first_point_trim = 25, \
|
||||
.second_point_trim = 85, \
|
||||
.default_temp_offset = 50, \
|
||||
.freq_tab[0] = { \
|
||||
.freq_clip_max = 800 * 1000, \
|
||||
.temp_level = 85, \
|
||||
}, \
|
||||
.freq_tab[1] = { \
|
||||
.freq_clip_max = 200 * 1000, \
|
||||
.temp_level = 103, \
|
||||
}, \
|
||||
.freq_tab_count = 2, \
|
||||
.registers = &exynos5260_tmu_registers, \
|
||||
|
||||
#define EXYNOS5260_TMU_DATA \
|
||||
__EXYNOS5260_TMU_DATA \
|
||||
.type = SOC_ARCH_EXYNOS5260, \
|
||||
.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
|
||||
TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
|
||||
TMU_SUPPORT_EMUL_TIME)
|
||||
|
||||
struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
|
||||
.tmu_data = {
|
||||
{ EXYNOS5260_TMU_DATA },
|
||||
{ EXYNOS5260_TMU_DATA },
|
||||
{ EXYNOS5260_TMU_DATA },
|
||||
{ EXYNOS5260_TMU_DATA },
|
||||
{ EXYNOS5260_TMU_DATA },
|
||||
},
|
||||
.tmu_count = 5,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5420)
|
||||
static const struct exynos_tmu_registers exynos5420_tmu_registers = {
|
||||
.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
|
||||
.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
|
||||
.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
|
||||
.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
|
||||
.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
|
||||
.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
|
||||
.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
|
||||
.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
|
||||
.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
|
||||
.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
|
||||
.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
|
||||
.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
|
||||
.tmu_status = EXYNOS_TMU_REG_STATUS,
|
||||
.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
|
||||
.threshold_th0 = EXYNOS_THD_TEMP_RISE,
|
||||
.threshold_th1 = EXYNOS_THD_TEMP_FALL,
|
||||
.tmu_inten = EXYNOS_TMU_REG_INTEN,
|
||||
.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
|
||||
.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
|
||||
.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
|
||||
/* INTEN_RISE3 Not availble in exynos5420 */
|
||||
.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
|
||||
.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
|
||||
.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
|
||||
.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
|
||||
.intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
|
||||
.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
|
||||
.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
|
||||
.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
|
||||
.emul_con = EXYNOS_EMUL_CON,
|
||||
.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
|
||||
.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
|
||||
.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
|
||||
};
|
||||
|
||||
#define __EXYNOS5420_TMU_DATA \
|
||||
.threshold_falling = 10, \
|
||||
.trigger_levels[0] = 85, \
|
||||
.trigger_levels[1] = 103, \
|
||||
.trigger_levels[2] = 110, \
|
||||
.trigger_levels[3] = 120, \
|
||||
.trigger_enable[0] = true, \
|
||||
.trigger_enable[1] = true, \
|
||||
.trigger_enable[2] = true, \
|
||||
.trigger_enable[3] = false, \
|
||||
.trigger_type[0] = THROTTLE_ACTIVE, \
|
||||
.trigger_type[1] = THROTTLE_ACTIVE, \
|
||||
.trigger_type[2] = SW_TRIP, \
|
||||
.trigger_type[3] = HW_TRIP, \
|
||||
.max_trigger_level = 4, \
|
||||
.gain = 8, \
|
||||
.reference_voltage = 16, \
|
||||
.noise_cancel_mode = 4, \
|
||||
.cal_type = TYPE_ONE_POINT_TRIMMING, \
|
||||
.efuse_value = 55, \
|
||||
.min_efuse_value = 40, \
|
||||
.max_efuse_value = 100, \
|
||||
.first_point_trim = 25, \
|
||||
.second_point_trim = 85, \
|
||||
.default_temp_offset = 50, \
|
||||
.freq_tab[0] = { \
|
||||
.freq_clip_max = 800 * 1000, \
|
||||
.temp_level = 85, \
|
||||
}, \
|
||||
.freq_tab[1] = { \
|
||||
.freq_clip_max = 200 * 1000, \
|
||||
.temp_level = 103, \
|
||||
}, \
|
||||
.freq_tab_count = 2, \
|
||||
.registers = &exynos5420_tmu_registers, \
|
||||
|
||||
#define EXYNOS5420_TMU_DATA \
|
||||
__EXYNOS5420_TMU_DATA \
|
||||
.type = SOC_ARCH_EXYNOS5250, \
|
||||
.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
|
||||
TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
|
||||
TMU_SUPPORT_EMUL_TIME)
|
||||
|
||||
#define EXYNOS5420_TMU_DATA_SHARED \
|
||||
__EXYNOS5420_TMU_DATA \
|
||||
.type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
|
||||
.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
|
||||
TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
|
||||
TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
|
||||
|
||||
struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
|
||||
.tmu_data = {
|
||||
{ EXYNOS5420_TMU_DATA },
|
||||
{ EXYNOS5420_TMU_DATA },
|
||||
{ EXYNOS5420_TMU_DATA_SHARED },
|
||||
{ EXYNOS5420_TMU_DATA_SHARED },
|
||||
{ EXYNOS5420_TMU_DATA_SHARED },
|
||||
},
|
||||
.tmu_count = 5,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5440)
|
||||
static const struct exynos_tmu_registers exynos5440_tmu_registers = {
|
||||
.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
|
||||
|
|
@ -217,10 +408,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
|
|||
.threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
|
||||
.threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
|
||||
.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
|
||||
.inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
|
||||
.inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
|
||||
.inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
|
||||
.inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
|
||||
.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
|
||||
.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
|
||||
.inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
|
||||
|
|
@ -228,6 +415,10 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
|
|||
.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
|
||||
.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
|
||||
.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
|
||||
.intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
|
||||
.intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
|
||||
.intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
|
||||
.intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
|
||||
.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
|
||||
.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
|
||||
.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
|
||||
|
|
@ -255,7 +446,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
|
|||
.type = SOC_ARCH_EXYNOS5440, \
|
||||
.registers = &exynos5440_tmu_registers, \
|
||||
.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
|
||||
TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
|
||||
TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
|
||||
|
||||
struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
|
||||
.tmu_data = {
|
||||
|
|
|
|||
|
|
@ -69,9 +69,11 @@
|
|||
#define EXYNOS_TMU_RISE_INT_MASK 0x111
|
||||
#define EXYNOS_TMU_RISE_INT_SHIFT 0
|
||||
#define EXYNOS_TMU_FALL_INT_MASK 0x111
|
||||
#define EXYNOS_TMU_FALL_INT_SHIFT 12
|
||||
#define EXYNOS_TMU_CLEAR_RISE_INT 0x111
|
||||
#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
|
||||
#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT 12
|
||||
#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT 16
|
||||
#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT 4
|
||||
#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
|
||||
#define EXYNOS_TMU_TRIP_MODE_MASK 0x7
|
||||
#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
|
||||
|
|
@ -85,6 +87,7 @@
|
|||
#define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
|
||||
#define EXYNOS_TMU_INTEN_FALL1_SHIFT 20
|
||||
#define EXYNOS_TMU_INTEN_FALL2_SHIFT 24
|
||||
#define EXYNOS_TMU_INTEN_FALL3_SHIFT 28
|
||||
|
||||
#define EXYNOS_EMUL_TIME 0x57F0
|
||||
#define EXYNOS_EMUL_TIME_MASK 0xffff
|
||||
|
|
@ -95,6 +98,17 @@
|
|||
|
||||
#define EXYNOS_MAX_TRIGGER_PER_REG 4
|
||||
|
||||
/* Exynos5260 specific */
|
||||
#define EXYNOS_TMU_REG_CONTROL1 0x24
|
||||
#define EXYNOS5260_TMU_REG_INTEN 0xC0
|
||||
#define EXYNOS5260_TMU_REG_INTSTAT 0xC4
|
||||
#define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
|
||||
#define EXYNOS5260_TMU_CLEAR_RISE_INT 0x1111
|
||||
#define EXYNOS5260_TMU_CLEAR_FALL_INT (0x1111 << 16)
|
||||
#define EXYNOS5260_TMU_RISE_INT_MASK 0x1111
|
||||
#define EXYNOS5260_TMU_FALL_INT_MASK 0x1111
|
||||
#define EXYNOS5260_EMUL_CON 0x100
|
||||
|
||||
/* Exynos4412 specific */
|
||||
#define EXYNOS4412_MUX_ADDR_VALUE 6
|
||||
#define EXYNOS4412_MUX_ADDR_SHIFT 20
|
||||
|
|
@ -119,7 +133,6 @@
|
|||
#define EXYNOS5440_TMU_RISE_INT_MASK 0xf
|
||||
#define EXYNOS5440_TMU_RISE_INT_SHIFT 0
|
||||
#define EXYNOS5440_TMU_FALL_INT_MASK 0xf
|
||||
#define EXYNOS5440_TMU_FALL_INT_SHIFT 4
|
||||
#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
|
||||
#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
|
||||
#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
|
||||
|
|
@ -156,6 +169,20 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
|
|||
#define EXYNOS5250_TMU_DRV_DATA (NULL)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5260)
|
||||
extern struct exynos_tmu_init_data const exynos5260_default_tmu_data;
|
||||
#define EXYNOS5260_TMU_DRV_DATA (&exynos5260_default_tmu_data)
|
||||
#else
|
||||
#define EXYNOS5260_TMU_DRV_DATA (NULL)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5420)
|
||||
extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
|
||||
#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
|
||||
#else
|
||||
#define EXYNOS5420_TMU_DRV_DATA (NULL)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5440)
|
||||
extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
|
||||
#define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
|
||||
|
|
|
|||
|
|
@ -1248,7 +1248,7 @@ int ti_bandgap_probe(struct platform_device *pdev)
|
|||
clk_rate = clk_round_rate(bgp->div_clk,
|
||||
bgp->conf->sensors[0].ts_data->max_freq);
|
||||
if (clk_rate < bgp->conf->sensors[0].ts_data->min_freq ||
|
||||
clk_rate == 0xffffffff) {
|
||||
clk_rate <= 0) {
|
||||
ret = -ENODEV;
|
||||
dev_err(&pdev->dev, "wrong clock rate (%d)\n", clk_rate);
|
||||
goto put_clks;
|
||||
|
|
|
|||
Loading…
Reference in New Issue