Use proper abstractions in quirk_intel_irqbalance
Since we may not have a pci_dev for the device we need to access, we can't use pci_read_config_word. But raw_pci_read is an internal implementation detail; it's better to use the architected pci_bus_read_config_word interface. Using PCI_DEVFN instead of a mysterious constant helps reassure everyone that we really do intend to access device 8. [ Thanks to Grant Grundler for pointing out to me that this is exactly what the write immediately above this is doing -- enabling device 8 to respond to config space cycles. - Matthew Grant also says: "Can you also add a comment which points at the Intel documentation? The 'Intel E7320 Memory Controller Hub (MCH) Datasheet' at http://download.intel.com/design/chipsets/datashts/30300702.pdf Page 69 documents register F4h (DEVPRES1). And I just doubled checked that the 0xf4 register value is restored later in the quirk (obvious when you look at the code but not from the patch" so here it is. - Linus ] Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Acked-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -11,7 +11,7 @@
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static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
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{
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u8 config, rev;
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u32 word;
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u16 word;
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/* BIOS may enable hardware IRQ balancing for
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* E7520/E7320/E7525(revision ID 0x9 and below)
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@ -26,8 +26,11 @@ static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
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pci_read_config_byte(dev, 0xf4, &config);
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pci_write_config_byte(dev, 0xf4, config|0x2);
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/* read xTPR register */
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raw_pci_read(0, 0, 0x40, 0x4c, 2, &word);
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/*
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* read xTPR register. We may not have a pci_dev for device 8
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* because it might be hidden until the above write.
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*/
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pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
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if (!(word & (1 << 13))) {
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dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
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