pci:add support aer/pme interrupts with none MSI/MSI-X/INTx mode
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode. When chip support the aer/pme interrupts with none MSI/MSI-X/INTx mode, maybe there is interrupt line for aer pme etc. Search the interrupt number in the fdt file. Then fixup the dev->irq with it. Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>5.4-rM2-2.2.x-imx-squashed
parent
219d54332a
commit
958dafe933
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@ -26,8 +26,12 @@ Required properties:
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- reg: base addresses and lengths of the PCIe controller register blocks.
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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"intr": The interrupt that is asserted for controller interrupts
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- interrupt-names: It could include the following entries:
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"aer": Asserted for aer interrupt when chip support the aer interrupt with
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none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
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"pme": Asserted for pme interrupt when chip support the pme interrupt with
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none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
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......
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- fsl,pcie-scfg: Must include two entries.
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The first entry must be a link to the SCFG device node
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The second entry must be '0' or '1' based on physical PCIe controller index.
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@ -43,8 +47,9 @@ Example:
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reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
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0x40 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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interrupt-names = "intr";
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */
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<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
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interrupt-names = "aer", "pme";
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fsl,pcie-scfg = <&scfg 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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@ -12,11 +12,14 @@
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of_irq.h>
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#include <asm/mach-types.h>
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#include <asm/mach/map.h>
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#include <asm/mach/pci.h>
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#include "../../../drivers/pci/pcie/portdrv.h"
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static int debug_pci;
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/*
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@ -64,6 +67,47 @@ void pcibios_report_status(u_int status_mask, int warn)
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pcibios_bus_report_status(bus, status_mask, warn);
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}
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/*
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* Check device tree if the service interrupts are there
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*/
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int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
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{
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int ret, count = 0;
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struct device_node *np = NULL;
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if (dev->bus->dev.of_node)
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np = dev->bus->dev.of_node;
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if (np == NULL)
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return 0;
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if (!IS_ENABLED(CONFIG_OF_IRQ))
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return 0;
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/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
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* request irq for aer
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*/
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if (mask & PCIE_PORT_SERVICE_AER) {
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ret = of_irq_get_byname(np, "aer");
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if (ret > 0) {
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irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
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count++;
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}
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}
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if (mask & PCIE_PORT_SERVICE_PME) {
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ret = of_irq_get_byname(np, "pme");
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if (ret > 0) {
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irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
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count++;
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}
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}
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/* TODO: add more service interrupts if there it is in the device tree*/
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return count;
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}
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/*
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* We don't use this to fix the device, but initialisation of it.
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* It's not the correct use for this, but it works.
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@ -13,11 +13,14 @@
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#include <linux/mm.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci-ecam.h>
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#include <linux/slab.h>
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#include "../../../drivers/pci/pcie/portdrv.h"
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#ifdef CONFIG_ACPI
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/*
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* Try to assign the IRQ number when probing a new device
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@ -31,6 +34,47 @@ int pcibios_alloc_irq(struct pci_dev *dev)
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}
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#endif
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/*
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* Check device tree if the service interrupts are there
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*/
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int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
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{
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int ret, count = 0;
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struct device_node *np = NULL;
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if (dev->bus->dev.of_node)
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np = dev->bus->dev.of_node;
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if (np == NULL)
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return 0;
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if (!IS_ENABLED(CONFIG_OF_IRQ))
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return 0;
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/* If root port doesn't support MSI/MSI-X/INTx in RC mode,
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* request irq for aer
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*/
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if (mask & PCIE_PORT_SERVICE_AER) {
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ret = of_irq_get_byname(np, "aer");
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if (ret > 0) {
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irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
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count++;
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}
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}
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if (mask & PCIE_PORT_SERVICE_PME) {
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ret = of_irq_get_byname(np, "pme");
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if (ret > 0) {
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irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
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count++;
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}
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}
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/* TODO: add more service interrupts if there it is in the device tree*/
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return count;
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}
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/*
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* raw_pci_read/write - Platform-specific PCI config space access.
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*/
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@ -37,6 +37,20 @@ static void release_pcie_device(struct device *dev)
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kfree(to_pcie_device(dev));
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}
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/**
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* pcibios_check_service_irqs - check irqs in the device tree
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* @dev: PCI Express port to handle
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* @irqs: Array of irqs to populate
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* @mask: Bitmask of port capabilities returned by get_port_device_capability()
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*
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* Return value: 0 means no service irqs in the device tree
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*
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*/
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int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
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{
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return 0;
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}
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/*
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* Fill in *pme, *aer, *dpc with the relevant Interrupt Message Numbers if
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* services are enabled in "mask". Return the number of MSI/MSI-X vectors
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@ -165,10 +179,25 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)
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static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
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{
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int ret, i;
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int irq = -1;
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for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
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irqs[i] = -1;
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/* Check if some platforms owns independent irq pins for AER/PME etc.
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* Some platforms may own independent AER/PME interrupts and set
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* them in the device tree file.
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*/
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ret = pcibios_check_service_irqs(dev, irqs, mask);
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if (ret) {
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if (dev->irq)
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irq = dev->irq;
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for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
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if (irqs[i] == -1)
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irqs[i] = irq;
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return 0;
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}
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/*
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* If we support PME but can't use MSI/MSI-X for it, we have to
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* fall back to INTx or other interrupts, e.g., a system shared
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@ -2021,6 +2021,7 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) {}
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int pcibios_alloc_irq(struct pci_dev *dev);
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void pcibios_free_irq(struct pci_dev *dev);
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resource_size_t pcibios_default_alignment(void);
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int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
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#ifdef CONFIG_HIBERNATE_CALLBACKS
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extern struct dev_pm_ops pcibios_pm_ops;
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