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davinci-mcasp: use bitfield definitions for PDIR 

The current driver creates value for set/clr of PDIR using (x<<26) instead
of the #defines that are convieniently made available.

Update the driver to use the bitfield definitions of PDIR. There is no
functional change introduced by this patch.

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Reviewed-by: James Nuss <jamesnuss@nanometrics.ca>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
hifive-unleashed-5.1
Ben Gardiner 2011-04-21 14:19:02 -04:00 committed by Mark Brown
parent 049cfaaa47
commit 9595c8f035
1 changed files with 6 additions and 3 deletions
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9
sound/soc/davinci/davinci-mcasp.c
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@ -434,7 +434,8 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));
mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
ACLKX | AHCLKX | AFSX);
break;
case SND_SOC_DAIFMT_CBM_CFS:
/* codec is clock master and frame slave */
@ -444,7 +445,8 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x2d << 26));
mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
ACLKX | AFSX | ACLKR | AFSR);
break;
case SND_SOC_DAIFMT_CBM_CFM:
/* codec is clock and frame master */
@ -454,7 +456,8 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26));
mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
break;
default: