ath10k: remove 4-addr padding related hw_param configuration
hw_4addr_pad was added to handle different types of padding in 4-address rx frame. But this padding is not very specific to 4-address, it can happen even with three address + ethernet decap mode. Since the padding information can be obtained through Rx desc for QCA99X0 and newer chips, this hw_param is not needed any more. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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@ -60,7 +60,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.otp_exe_param = 0,
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.channel_counters_freq_hz = 88000,
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.max_probe_resp_desc_thres = 0,
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.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
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.cal_data_len = 2116,
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.fw = {
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.dir = QCA988X_HW_2_0_FW_DIR,
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@ -80,7 +79,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.otp_exe_param = 0,
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.channel_counters_freq_hz = 88000,
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.max_probe_resp_desc_thres = 0,
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.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
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.cal_data_len = 2116,
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.fw = {
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.dir = QCA9887_HW_1_0_FW_DIR,
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@ -117,7 +115,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.otp_exe_param = 0,
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.channel_counters_freq_hz = 88000,
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.max_probe_resp_desc_thres = 0,
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.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
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.cal_data_len = 8124,
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.fw = {
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.dir = QCA6174_HW_2_1_FW_DIR,
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@ -136,7 +133,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.otp_exe_param = 0,
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.channel_counters_freq_hz = 88000,
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.max_probe_resp_desc_thres = 0,
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.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
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.cal_data_len = 8124,
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.fw = {
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.dir = QCA6174_HW_3_0_FW_DIR,
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@ -155,7 +151,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.otp_exe_param = 0,
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.channel_counters_freq_hz = 88000,
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.max_probe_resp_desc_thres = 0,
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.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
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.cal_data_len = 8124,
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.fw = {
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/* uses same binaries as hw3.0 */
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@ -177,7 +172,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.cck_rate_map_rev2 = true,
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.channel_counters_freq_hz = 150000,
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.max_probe_resp_desc_thres = 24,
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.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
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.tx_chain_mask = 0xf,
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.rx_chain_mask = 0xf,
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.max_spatial_stream = 4,
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@ -202,7 +196,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.cck_rate_map_rev2 = true,
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.channel_counters_freq_hz = 150000,
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.max_probe_resp_desc_thres = 24,
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.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
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.tx_chain_mask = 0xf,
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.rx_chain_mask = 0xf,
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.max_spatial_stream = 4,
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@ -226,7 +219,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.continuous_frag_desc = true,
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.channel_counters_freq_hz = 150000,
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.max_probe_resp_desc_thres = 24,
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.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
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.tx_chain_mask = 3,
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.rx_chain_mask = 3,
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.max_spatial_stream = 2,
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@ -288,7 +280,6 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.cck_rate_map_rev2 = true,
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.channel_counters_freq_hz = 125000,
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.max_probe_resp_desc_thres = 24,
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.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
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.tx_chain_mask = 0x3,
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.rx_chain_mask = 0x3,
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.max_spatial_stream = 2,
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@ -338,11 +338,6 @@ enum ath10k_hw_rate_rev2_cck {
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ATH10K_HW_RATE_REV2_CCK_SP_11M,
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};
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enum ath10k_hw_4addr_pad {
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ATH10K_HW_4ADDR_PAD_AFTER,
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ATH10K_HW_4ADDR_PAD_BEFORE,
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};
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enum ath10k_hw_cc_wraparound_type {
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ATH10K_HW_CC_WRAP_DISABLED = 0,
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@ -395,9 +390,6 @@ struct ath10k_hw_params {
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*/
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u32 max_probe_resp_desc_thres;
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/* The padding bytes's location is different on various chips */
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enum ath10k_hw_4addr_pad hw_4addr_pad;
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u32 tx_chain_mask;
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u32 rx_chain_mask;
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u32 max_spatial_stream;
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