arm: mach-mv78xx0: convert to use the mvebu-mbus driver
This commit convers the mach-mv78xx0 sub-architecture to use the mvebu-mbus driver. We simply have to call mvebu_mbus_init() in the ->init_early() function, and modify the PCIe code so that it uses the new functions provided by mvebu-mbus to create the needed PCIe windows. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jason Cooper <jason@lakedaemon.net>hifive-unleashed-5.1
Thomas Petazzoni
Jason Cooper
parent
5d1190ea69
commit
95b80e0a9a
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@ -588,6 +588,7 @@ config ARCH_MV78XX0
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select GENERIC_CLOCKEVENTS
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select PCI
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select PLAT_ORION_LEGACY
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select MVEBU_MBUS
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help
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Support for the following Marvell MV78xx0 series SoCs:
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MV781x0, MV782x0.
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@ -1,4 +1,4 @@
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obj-y += common.o addr-map.o mpp.o irq.o pcie.o
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obj-y += common.o mpp.o irq.o pcie.o
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obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o
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obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o
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obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o
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@ -1,93 +0,0 @@
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/*
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* arch/arm/mach-mv78xx0/addr-map.c
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*
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* Address map functions for Marvell MV78xx0 SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <plat/addr-map.h>
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#include <mach/mv78xx0.h>
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#include "common.h"
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DEV_BUS 1
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#define TARGET_PCIE0 4
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#define TARGET_PCIE1 8
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#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
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#define ATTR_DEV_SPI_ROM 0x1f
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#define ATTR_DEV_BOOT 0x2f
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#define ATTR_DEV_CS3 0x37
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#define ATTR_DEV_CS2 0x3b
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#define ATTR_DEV_CS1 0x3d
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#define ATTR_DEV_CS0 0x3e
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#define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l)))
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#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l)))
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/*
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* CPU Address Decode Windows registers
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*/
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#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
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#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
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static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
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{
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/*
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* Find the control register base address for this window.
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*
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* BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
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* MBUS bridge depending on which CPU core we're running on,
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* so we don't need to take that into account here.
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*/
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return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
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}
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/*
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* Description of the windows needed by the platform code
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*/
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static struct orion_addr_map_cfg addr_map_cfg __initdata = {
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.num_wins = 14,
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.remappable_wins = 8,
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.win_cfg_base = win_cfg_base,
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};
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void __init mv78xx0_setup_cpu_mbus(void)
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{
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/*
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* Disable, clear and configure windows.
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*/
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orion_config_wins(&addr_map_cfg, NULL);
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/*
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* Setup MBUS dram target info.
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*/
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if (mv78xx0_core_index() == 0)
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orion_setup_cpu_mbus_target(&addr_map_cfg,
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(void __iomem *) DDR_WINDOW_CPU0_BASE);
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else
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orion_setup_cpu_mbus_target(&addr_map_cfg,
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(void __iomem *) DDR_WINDOW_CPU1_BASE);
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}
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void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
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int maj, int min)
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{
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orion_setup_cpu_win(&addr_map_cfg, window, base, size,
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TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
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}
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void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
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int maj, int min)
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{
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orion_setup_cpu_win(&addr_map_cfg, window, base, size,
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TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
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}
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@ -334,6 +334,14 @@ void __init mv78xx0_uart3_init(void)
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void __init mv78xx0_init_early(void)
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{
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orion_time_set_base(TIMER_VIRT_BASE);
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if (mv78xx0_core_index() == 0)
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mvebu_mbus_init("marvell,mv78xx0-mbus",
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BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,
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DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);
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else
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mvebu_mbus_init("marvell,mv78xx0-mbus",
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BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,
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DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);
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}
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void __init_refok mv78xx0_timer_init(void)
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@ -397,8 +405,6 @@ void __init mv78xx0_init(void)
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printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
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printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
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mv78xx0_setup_cpu_mbus();
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#ifdef CONFIG_CACHE_FEROCEON_L2
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feroceon_l2_init(is_l2_writethrough());
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#endif
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@ -60,13 +60,18 @@
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*/
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#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
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#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE)
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#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE)
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#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE)
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#define BRIDGE_WINS_SZ (0xA000)
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/*
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* Register Map
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*/
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#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
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#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500)
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#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570)
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#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000)
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#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500)
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#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570)
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#define DDR_WINDOW_CPU_SZ (0x20)
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#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
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#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
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@ -10,11 +10,11 @@
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/mbus.h>
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#include <video/vga.h>
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#include <asm/irq.h>
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#include <asm/mach/pci.h>
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#include <plat/pcie.h>
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#include <plat/addr-map.h>
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#include <mach/mv78xx0.h>
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#include "common.h"
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@ -54,7 +54,6 @@ static void __init mv78xx0_pcie_preinit(void)
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int i;
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u32 size_each;
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u32 start;
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int win = 0;
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pcie_io_space.name = "PCIe I/O Space";
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pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
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@ -72,6 +71,7 @@ static void __init mv78xx0_pcie_preinit(void)
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start = MV78XX0_PCIE_MEM_PHYS_BASE;
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for (i = 0; i < num_pcie_ports; i++) {
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struct pcie_port *pp = pcie_port + i;
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char winname[MVEBU_MBUS_MAX_WINNAME_SZ];
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snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
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"PCIe %d.%d MEM", pp->maj, pp->min);
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@ -85,12 +85,17 @@ static void __init mv78xx0_pcie_preinit(void)
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if (request_resource(&iomem_resource, &pp->res))
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panic("can't allocate PCIe MEM sub-space");
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mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start,
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resource_size(&pp->res),
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pp->maj, pp->min);
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snprintf(winname, sizeof(winname), "pcie%d.%d",
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pp->maj, pp->min);
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mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K,
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pp->maj, pp->min);
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mvebu_mbus_add_window_remap_flags(winname,
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pp->res.start,
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resource_size(&pp->res),
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MVEBU_MBUS_NO_REMAP,
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MVEBU_MBUS_PCI_MEM);
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mvebu_mbus_add_window_remap_flags(winname,
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i * SZ_64K, SZ_64K,
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0, MVEBU_MBUS_PCI_IO);
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}
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}
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@ -3,8 +3,6 @@
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#
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ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
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obj-$(CONFIG_ARCH_MV78XX0) += addr-map.o
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orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
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obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o
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obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y)
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@ -43,6 +43,9 @@ struct mbus_dram_target_info
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*/
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#define MVEBU_MBUS_NO_REMAP (0xffffffff)
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/* Maximum size of a mbus window name */
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#define MVEBU_MBUS_MAX_WINNAME_SZ 32
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/*
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* The Marvell mbus is to be found only on SOCs from the Orion family
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* at the moment. Provide a dummy stub for other architectures.
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