drm/amdgpu: add initial vcn support and decode tests
VCN is the new media block on Raven. Add core support and the ring and ib tests for decode. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>hifive-unleashed-5.1
Leo Liu
Alex Deucher
parent
9e2837f6ae
commit
95d0906f85
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@ -93,6 +93,10 @@ amdgpu-y += \
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vce_v3_0.o \
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vce_v4_0.o
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# add VCN block
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amdgpu-y += \
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amdgpu_vcn.o
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# add amdkfd interfaces
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amdgpu-y += \
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amdgpu_amdkfd.o \
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@ -1180,6 +1180,31 @@ void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
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void amdgpu_get_pcie_info(struct amdgpu_device *adev);
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/*
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* VCN
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*/
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#define AMDGPU_VCN_STACK_SIZE (200*1024)
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#define AMDGPU_VCN_HEAP_SIZE (256*1024)
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#define AMDGPU_VCN_SESSION_SIZE (50*1024)
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#define AMDGPU_VCN_FIRMWARE_OFFSET 256
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#define AMDGPU_VCN_MAX_ENC_RINGS 3
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struct amdgpu_vcn {
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struct amdgpu_bo *vcpu_bo;
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void *cpu_addr;
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uint64_t gpu_addr;
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unsigned fw_version;
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void *saved_bo;
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struct delayed_work idle_work;
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const struct firmware *fw; /* VCN firmware */
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struct amdgpu_ring ring_dec;
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struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
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struct amdgpu_irq_src irq;
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struct amd_sched_entity entity_dec;
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struct amd_sched_entity entity_enc;
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uint32_t srbm_soft_reset;
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};
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/*
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* SDMA
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*/
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@ -1572,11 +1597,18 @@ struct amdgpu_device {
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/* sdma */
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struct amdgpu_sdma sdma;
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/* uvd */
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struct amdgpu_uvd uvd;
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union {
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struct {
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/* uvd */
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struct amdgpu_uvd uvd;
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/* vce */
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struct amdgpu_vce vce;
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/* vce */
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struct amdgpu_vce vce;
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};
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/* vcn */
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struct amdgpu_vcn vcn;
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};
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/* firmwares */
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struct amdgpu_firmware firmware;
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@ -0,0 +1,425 @@
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <drm/drmP.h>
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#include <drm/drm.h>
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#include "amdgpu.h"
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#include "amdgpu_pm.h"
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#include "amdgpu_vcn.h"
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#include "soc15d.h"
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#include "soc15_common.h"
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#include "vega10/soc15ip.h"
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#include "raven1/VCN/vcn_1_0_offset.h"
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/* 1 second timeout */
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#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
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/* Firmware Names */
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#define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
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MODULE_FIRMWARE(FIRMWARE_RAVEN);
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static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
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int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring;
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struct amd_sched_rq *rq;
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unsigned long bo_size;
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const char *fw_name;
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const struct common_firmware_header *hdr;
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unsigned version_major, version_minor, family_id;
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int r;
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INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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fw_name = FIRMWARE_RAVEN;
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break;
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default:
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return -EINVAL;
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}
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r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
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if (r) {
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dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
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fw_name);
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return r;
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}
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r = amdgpu_ucode_validate(adev->vcn.fw);
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if (r) {
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dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n",
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fw_name);
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release_firmware(adev->vcn.fw);
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adev->vcn.fw = NULL;
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return r;
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}
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hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
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family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
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version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
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version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
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DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
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version_major, version_minor, family_id);
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bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
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+ AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
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+ AMDGPU_VCN_SESSION_SIZE * 40;
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r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
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&adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
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if (r) {
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dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
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return r;
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}
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ring = &adev->vcn.ring_dec;
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rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
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r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_dec,
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rq, amdgpu_sched_jobs);
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if (r != 0) {
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DRM_ERROR("Failed setting up VCN dec run queue.\n");
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return r;
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}
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return 0;
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}
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int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
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{
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kfree(adev->vcn.saved_bo);
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amd_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec);
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amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
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&adev->vcn.gpu_addr,
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(void **)&adev->vcn.cpu_addr);
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amdgpu_ring_fini(&adev->vcn.ring_dec);
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release_firmware(adev->vcn.fw);
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return 0;
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}
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int amdgpu_vcn_suspend(struct amdgpu_device *adev)
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{
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unsigned size;
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void *ptr;
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if (adev->vcn.vcpu_bo == NULL)
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return 0;
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cancel_delayed_work_sync(&adev->vcn.idle_work);
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size = amdgpu_bo_size(adev->vcn.vcpu_bo);
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ptr = adev->vcn.cpu_addr;
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adev->vcn.saved_bo = kmalloc(size, GFP_KERNEL);
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if (!adev->vcn.saved_bo)
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return -ENOMEM;
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memcpy_fromio(adev->vcn.saved_bo, ptr, size);
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return 0;
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}
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int amdgpu_vcn_resume(struct amdgpu_device *adev)
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{
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unsigned size;
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void *ptr;
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if (adev->vcn.vcpu_bo == NULL)
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return -EINVAL;
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size = amdgpu_bo_size(adev->vcn.vcpu_bo);
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ptr = adev->vcn.cpu_addr;
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if (adev->vcn.saved_bo != NULL) {
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memcpy_toio(ptr, adev->vcn.saved_bo, size);
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kfree(adev->vcn.saved_bo);
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adev->vcn.saved_bo = NULL;
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} else {
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const struct common_firmware_header *hdr;
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unsigned offset;
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hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
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offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
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memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
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le32_to_cpu(hdr->ucode_size_bytes));
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size -= le32_to_cpu(hdr->ucode_size_bytes);
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ptr += le32_to_cpu(hdr->ucode_size_bytes);
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memset_io(ptr, 0, size);
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}
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return 0;
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}
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static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
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bool direct, struct dma_fence **fence)
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{
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struct ttm_validate_buffer tv;
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struct ww_acquire_ctx ticket;
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struct list_head head;
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struct amdgpu_job *job;
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struct amdgpu_ib *ib;
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struct dma_fence *f = NULL;
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struct amdgpu_device *adev = ring->adev;
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uint64_t addr;
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int i, r;
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memset(&tv, 0, sizeof(tv));
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tv.bo = &bo->tbo;
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INIT_LIST_HEAD(&head);
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list_add(&tv.head, &head);
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r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
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if (r)
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return r;
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r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
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if (r)
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goto err;
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r = amdgpu_job_alloc_with_ib(adev, 64, &job);
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if (r)
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goto err;
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ib = &job->ibs[0];
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addr = amdgpu_bo_gpu_offset(bo);
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ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0);
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ib->ptr[1] = addr;
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ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0);
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ib->ptr[3] = addr >> 32;
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ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0);
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ib->ptr[5] = 0;
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for (i = 6; i < 16; i += 2) {
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ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0);
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ib->ptr[i+1] = 0;
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}
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ib->length_dw = 16;
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if (direct) {
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r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
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job->fence = dma_fence_get(f);
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if (r)
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goto err_free;
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amdgpu_job_free(job);
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} else {
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r = amdgpu_job_submit(job, ring, &adev->vcn.entity_dec,
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AMDGPU_FENCE_OWNER_UNDEFINED, &f);
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if (r)
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goto err_free;
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}
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ttm_eu_fence_buffer_objects(&ticket, &head, f);
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if (fence)
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*fence = dma_fence_get(f);
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amdgpu_bo_unref(&bo);
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dma_fence_put(f);
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return 0;
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err_free:
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amdgpu_job_free(job);
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err:
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ttm_eu_backoff_reservation(&ticket, &head);
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return r;
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}
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static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
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struct dma_fence **fence)
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{
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_bo *bo;
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uint32_t *msg;
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int r, i;
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r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
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AMDGPU_GEM_DOMAIN_VRAM,
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AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
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AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
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NULL, NULL, &bo);
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if (r)
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return r;
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r = amdgpu_bo_reserve(bo, false);
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if (r) {
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amdgpu_bo_unref(&bo);
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return r;
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}
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r = amdgpu_bo_kmap(bo, (void **)&msg);
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if (r) {
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amdgpu_bo_unreserve(bo);
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amdgpu_bo_unref(&bo);
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return r;
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}
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/* stitch together an vcn create msg */
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msg[0] = cpu_to_le32(0x00000de4);
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msg[1] = cpu_to_le32(0x00000000);
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msg[2] = cpu_to_le32(handle);
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msg[3] = cpu_to_le32(0x00000000);
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msg[4] = cpu_to_le32(0x00000000);
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msg[5] = cpu_to_le32(0x00000000);
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msg[6] = cpu_to_le32(0x00000000);
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msg[7] = cpu_to_le32(0x00000780);
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msg[8] = cpu_to_le32(0x00000440);
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msg[9] = cpu_to_le32(0x00000000);
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msg[10] = cpu_to_le32(0x01b37000);
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for (i = 11; i < 1024; ++i)
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msg[i] = cpu_to_le32(0x0);
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amdgpu_bo_kunmap(bo);
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amdgpu_bo_unreserve(bo);
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return amdgpu_vcn_dec_send_msg(ring, bo, true, fence);
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}
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static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
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bool direct, struct dma_fence **fence)
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{
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_bo *bo;
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uint32_t *msg;
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int r, i;
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r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
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AMDGPU_GEM_DOMAIN_VRAM,
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AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
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AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
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NULL, NULL, &bo);
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if (r)
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return r;
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r = amdgpu_bo_reserve(bo, false);
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if (r) {
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amdgpu_bo_unref(&bo);
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return r;
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}
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r = amdgpu_bo_kmap(bo, (void **)&msg);
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if (r) {
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amdgpu_bo_unreserve(bo);
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amdgpu_bo_unref(&bo);
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return r;
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}
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/* stitch together an vcn destroy msg */
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msg[0] = cpu_to_le32(0x00000de4);
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msg[1] = cpu_to_le32(0x00000002);
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msg[2] = cpu_to_le32(handle);
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msg[3] = cpu_to_le32(0x00000000);
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for (i = 4; i < 1024; ++i)
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msg[i] = cpu_to_le32(0x0);
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amdgpu_bo_kunmap(bo);
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amdgpu_bo_unreserve(bo);
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return amdgpu_vcn_dec_send_msg(ring, bo, direct, fence);
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}
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static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
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{
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struct amdgpu_device *adev =
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container_of(work, struct amdgpu_device, vcn.idle_work.work);
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unsigned fences = amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
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if (fences == 0) {
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if (adev->pm.dpm_enabled) {
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amdgpu_dpm_enable_uvd(adev, false);
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} else {
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amdgpu_asic_set_uvd_clocks(adev, 0, 0);
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}
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} else {
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schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
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}
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}
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void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
|
||||
bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
|
||||
|
||||
if (set_clocks) {
|
||||
if (adev->pm.dpm_enabled) {
|
||||
amdgpu_dpm_enable_uvd(adev, true);
|
||||
} else {
|
||||
amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
|
||||
{
|
||||
schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
|
||||
}
|
||||
|
||||
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
|
||||
{
|
||||
struct dma_fence *fence;
|
||||
long r;
|
||||
|
||||
r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
|
||||
if (r) {
|
||||
DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
|
||||
goto error;
|
||||
}
|
||||
|
||||
r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, true, &fence);
|
||||
if (r) {
|
||||
DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
|
||||
goto error;
|
||||
}
|
||||
|
||||
r = dma_fence_wait_timeout(fence, false, timeout);
|
||||
if (r == 0) {
|
||||
DRM_ERROR("amdgpu: IB test timed out.\n");
|
||||
r = -ETIMEDOUT;
|
||||
} else if (r < 0) {
|
||||
DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
|
||||
} else {
|
||||
DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
|
||||
r = 0;
|
||||
}
|
||||
|
||||
dma_fence_put(fence);
|
||||
|
||||
error:
|
||||
return r;
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __AMDGPU_VCN_H__
|
||||
#define __AMDGPU_VCN_H__
|
||||
|
||||
int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
|
||||
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
|
||||
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
|
||||
int amdgpu_vcn_resume(struct amdgpu_device *adev);
|
||||
void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
|
||||
void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
|
||||
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue