i2c: omap: re-factor omap_i2c_init function
re-factor omap_i2c_init() so that we can re-use it for resume. While at it also remove the bufstate variable as we write it in omap_i2c_resize_fifo for every transfer. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
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@ -210,7 +210,6 @@ struct omap_i2c_dev {
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u16 pscstate;
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u16 scllstate;
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u16 sclhstate;
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u16 bufstate;
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u16 syscstate;
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u16 westate;
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u16 errata;
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@ -278,9 +277,34 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
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(i2c_dev->regs[reg] << i2c_dev->reg_shift));
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}
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static void __omap_i2c_init(struct omap_i2c_dev *dev)
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{
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
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/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
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omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
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/* SCL low and high time values */
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omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
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omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
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if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
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omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
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/* Take the I2C module out of reset: */
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
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/*
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* Don't write to this register if the IE state is 0 as it can
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* cause deadlock.
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*/
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if (dev->iestate)
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omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
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}
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static int omap_i2c_init(struct omap_i2c_dev *dev)
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{
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u16 psc = 0, scll = 0, sclh = 0, buf = 0;
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u16 psc = 0, scll = 0, sclh = 0;
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u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
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unsigned long fclk_rate = 12000000;
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unsigned long timeout;
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@ -330,11 +354,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
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* REVISIT: Some wkup sources might not be needed.
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*/
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dev->westate = OMAP_I2C_WE_ALL;
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omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
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dev->westate);
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}
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}
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
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if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
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/*
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@ -419,28 +440,17 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
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sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
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}
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/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
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omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
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/* SCL low and high time values */
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omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
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omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
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/* Take the I2C module out of reset: */
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omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
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/* Enable interrupts */
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dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
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OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
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OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
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(OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
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omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
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if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
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dev->pscstate = psc;
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dev->scllstate = scll;
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dev->sclhstate = sclh;
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dev->bufstate = buf;
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}
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dev->pscstate = psc;
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dev->scllstate = scll;
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dev->sclhstate = sclh;
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__omap_i2c_init(dev);
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return 0;
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}
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@ -1308,23 +1318,8 @@ static int omap_i2c_runtime_resume(struct device *dev)
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if (!_dev->regs)
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return 0;
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if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
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omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
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omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
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omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
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omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
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omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
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omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
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omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
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omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
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}
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/*
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* Don't write to this register if the IE state is 0 as it can
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* cause deadlock.
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*/
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if (_dev->iestate)
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omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate);
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if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE)
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__omap_i2c_init(_dev);
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return 0;
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}
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