ARM: dts: stm32: Introduce new STM32MP15 SOCs: STM32MP151 and STM32MP153
STM32MP151 and STM32MP153 were not explicitly supported through stm32mp157c.dts. This commit adds dedicated files to support all STM32MP15 SOCs family. The differences between those SOCs are: -STM32MP151 [1]: common file. -STM32MP153 [2]: STM32MP151 + CANs + a second CortexA7-CPU. -STM32MP157 [3]: STM32MP153 + DSI + GPU. [1] https://www.st.com/resource/en/reference_manual/dm00366349.pdf [2] https://www.st.com/resource/en/reference_manual/dm00366355.pdf [3] https://www.st.com/resource/en/reference_manual/dm00327659.pdf Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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Alexandre Torgue
parent
48c7181fa7
commit
95e395c881
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@ -20,12 +20,6 @@
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device_type = "cpu";
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reg = <0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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psci {
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@ -953,32 +947,6 @@
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};
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};
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m_can1: can@4400e000 {
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compatible = "bosch,m_can";
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reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
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status = "disabled";
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};
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m_can2: can@4400f000 {
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compatible = "bosch,m_can";
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reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
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status = "disabled";
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};
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dma1: dma@48000000 {
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compatible = "st,stm32-dma";
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reg = <0x48000000 0x400>;
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@ -1444,26 +1412,6 @@
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status = "disabled";
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};
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gpu: gpu@59000000 {
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compatible = "vivante,gc";
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reg = <0x59000000 0x800>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc GPU>, <&rcc GPU_K>;
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clock-names = "bus" ,"core";
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resets = <&rcc GPU_R>;
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status = "disabled";
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};
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dsi: dsi@5a000000 {
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compatible = "st,stm32-dsi";
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reg = <0x5a000000 0x800>;
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clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
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clock-names = "pclk", "ref", "px_clk";
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resets = <&rcc DSI_R>;
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reset-names = "apb";
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status = "disabled";
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};
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ltdc: display-controller@5a001000 {
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compatible = "st,stm32-ltdc";
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reg = <0x5a001000 0x400>;
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45
arch/arm/boot/dts/stm32mp153.dtsi
Normal file
45
arch/arm/boot/dts/stm32mp153.dtsi
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@ -0,0 +1,45 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
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*/
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#include "stm32mp151.dtsi"
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/ {
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cpus {
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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soc {
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m_can1: can@4400e000 {
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compatible = "bosch,m_can";
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reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
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status = "disabled";
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};
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m_can2: can@4400f000 {
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compatible = "bosch,m_can";
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reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
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status = "disabled";
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};
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};
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};
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31
arch/arm/boot/dts/stm32mp157.dtsi
Normal file
31
arch/arm/boot/dts/stm32mp157.dtsi
Normal file
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@ -0,0 +1,31 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
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*/
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#include "stm32mp153.dtsi"
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/ {
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soc {
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gpu: gpu@59000000 {
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compatible = "vivante,gc";
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reg = <0x59000000 0x800>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc GPU>, <&rcc GPU_K>;
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clock-names = "bus" ,"core";
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resets = <&rcc GPU_R>;
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status = "disabled";
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};
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dsi: dsi@5a000000 {
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compatible = "st,stm32-dsi";
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reg = <0x5a000000 0x800>;
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clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
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clock-names = "pclk", "ref", "px_clk";
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resets = <&rcc DSI_R>;
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reset-names = "apb";
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status = "disabled";
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};
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};
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};
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@ -6,7 +6,7 @@
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/dts-v1/;
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#include "stm32mp157c.dtsi"
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#include "stm32mp157.dtsi"
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#include "stm32mp15-pinctrl.dtsi"
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#include "stm32mp15xxac-pinctrl.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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@ -6,7 +6,7 @@
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/dts-v1/;
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#include "stm32mp157c.dtsi"
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#include "stm32mp157.dtsi"
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#include "stm32mp15-pinctrl.dtsi"
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#include "stm32mp15xxac-pinctrl.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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@ -5,7 +5,7 @@
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*/
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/dts-v1/;
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#include "stm32mp157c.dtsi"
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#include "stm32mp157.dtsi"
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#include "stm32mp15-pinctrl.dtsi"
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#include "stm32mp15xxaa-pinctrl.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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