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drm/i915/perf: fix ICL perf register offsets 

We got the wrong offsets (could they have changed?). New values were
computed off an error state by looking up the register offset in the
context image as written by the HW.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1de401c08f ("drm/i915/perf: enable perf support on ICL")
Cc: <stable@vger.kernel.org> # v4.18+
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190610081914.25428-1-lionel.g.landwerlin@intel.com
(cherry picked from commit 8dcfdfb450)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
alistair/sunxi64-5.4-dsi
Lionel Landwerlin 2019-06-10 11:19:14 +03:00 committed by Jani Nikula
parent 248f883db6
commit 95eef14cda
1 changed files with 7 additions and 3 deletions
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10
drivers/gpu/drm/i915/i915_perf.c
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@ -3477,9 +3477,13 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
dev_priv->perf.oa.ops.disable_metric_set = gen10_disable_metric_set;
dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
if (IS_GEN(dev_priv, 10)) {
dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
} else {
dev_priv->perf.oa.ctx_oactxctrl_offset = 0x124;
dev_priv->perf.oa.ctx_flexeu0_offset = 0x78e;
}
dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
}
}