pinctrl: sunrisepoint: Fix PAD lock register offset for SPT-H
[ Upstream commit5.4-rM2-2.2.x-imx-squashed6b7275c877
] It appears that SPT-H variant has different offset for PAD locking registers. Fix it here. Fixes:551fa5801e
("pinctrl: intel: sunrisepoint: Add Intel Sunrisepoint-H support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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e529b8db96
commit
960d609dd4
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@ -15,17 +15,18 @@
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#include "pinctrl-intel.h"
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#define SPT_PAD_OWN 0x020
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#define SPT_PADCFGLOCK 0x0a0
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#define SPT_HOSTSW_OWN 0x0d0
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#define SPT_GPI_IS 0x100
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#define SPT_GPI_IE 0x120
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#define SPT_PAD_OWN 0x020
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#define SPT_H_PADCFGLOCK 0x090
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#define SPT_LP_PADCFGLOCK 0x0a0
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#define SPT_HOSTSW_OWN 0x0d0
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#define SPT_GPI_IS 0x100
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#define SPT_GPI_IE 0x120
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#define SPT_COMMUNITY(b, s, e) \
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{ \
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.barno = (b), \
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.padown_offset = SPT_PAD_OWN, \
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.padcfglock_offset = SPT_PADCFGLOCK, \
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.padcfglock_offset = SPT_LP_PADCFGLOCK, \
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.hostown_offset = SPT_HOSTSW_OWN, \
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.is_offset = SPT_GPI_IS, \
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.ie_offset = SPT_GPI_IE, \
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@ -47,7 +48,7 @@
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{ \
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.barno = (b), \
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.padown_offset = SPT_PAD_OWN, \
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.padcfglock_offset = SPT_PADCFGLOCK, \
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.padcfglock_offset = SPT_H_PADCFGLOCK, \
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.hostown_offset = SPT_HOSTSW_OWN, \
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.is_offset = SPT_GPI_IS, \
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.ie_offset = SPT_GPI_IE, \
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