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iMX51: introduce IMX_GPIO_NR

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Currently, to define a GPIO number, we're using something like :

#define EFIKAMX_PCBID0         (2*32 + 16)

to define GPIO 3 16.

This is not really readable and it's error prone imho (note the 3 vs 2).
So, I'm introducing a new macro to define this in a better way. Now, the
code sample become :

#define EFIKAMX_PCBID0         IMX_GPIO_NR(3, 16)

v2:
- move to gpio.h
- add parens & spaces
- switch to IMX_GPIO_NR instead of MX51_GPIO_NR

Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Arnaud Patard (Rtp) 2010-11-26 15:20:52 +01:00 committed by Sascha Hauer
parent b99545cb59
commit 96886c4361
7 changed files with 49 additions and 44 deletions
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10
arch/arm/mach-mx5/board-cpuimx51.c
View file

@ -40,11 +40,11 @@
#include "devices-imx51.h"
#include "devices.h"
#define CPUIMX51_USBH1_STP (0*32 + 27)
#define CPUIMX51_QUARTA_GPIO (2*32 + 28)
#define CPUIMX51_QUARTB_GPIO (2*32 + 25)
#define CPUIMX51_QUARTC_GPIO (2*32 + 26)
#define CPUIMX51_QUARTD_GPIO (2*32 + 27)
#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27)
#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28)
#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25)
#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26)
#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27)
#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)

28
arch/arm/mach-mx5/board-cpuimx51sd.c
View file

@ -43,19 +43,19 @@
#include "devices-imx51.h"
#include "devices.h"
#define USBH1_RST (1*32 + 28)
#define ETH_RST (1*32 + 31)
#define TSC2007_IRQGPIO (2*32 + 12)
#define CAN_IRQGPIO (0*32 + 1)
#define CAN_RST (3*32 + 15)
#define CAN_NCS (3*32 + 24)
#define CAN_RXOBF (0*32 + 4)
#define CAN_RX1BF (0*32 + 6)
#define CAN_TXORTS (0*32 + 7)
#define CAN_TX1RTS (0*32 + 8)
#define CAN_TX2RTS (0*32 + 9)
#define I2C_SCL (3*32 + 16)
#define I2C_SDA (3*32 + 17)
#define USBH1_RST IMX_GPIO_NR(2, 28)
#define ETH_RST IMX_GPIO_NR(2, 31)
#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12)
#define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
#define CAN_RST IMX_GPIO_NR(4, 15)
#define CAN_NCS IMX_GPIO_NR(4, 24)
#define CAN_RXOBF IMX_GPIO_NR(1, 4)
#define CAN_RX1BF IMX_GPIO_NR(1, 6)
#define CAN_TXORTS IMX_GPIO_NR(1, 7)
#define CAN_TX1RTS IMX_GPIO_NR(1, 8)
#define CAN_TX2RTS IMX_GPIO_NR(1, 9)
#define I2C_SCL IMX_GPIO_NR(4, 16)
#define I2C_SDA IMX_GPIO_NR(4, 17)
/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET 0x10
@ -243,7 +243,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
.mode = SPI_MODE_0,
.chip_select = 0,
.platform_data = &mcp251x_info,
.irq = gpio_to_irq(0 * 32 + 1)
.irq = gpio_to_irq(CAN_IRQGPIO)
},
};

14
arch/arm/mach-mx5/board-mx51_babbage.c
View file

@ -38,13 +38,13 @@
#include "devices.h"
#include "cpu_op-mx51.h"
#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */
#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */
#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */
#define BABBAGE_ECSPI1_CS0 (3*32 + 24) /* GPIO_4_24 */
#define BABBAGE_ECSPI1_CS1 (3*32 + 25) /* GPIO_4_25 */
#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
#define BABBAGE_PHY_RESET IMX_GPIO_NR(2, 5)
#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET 0x10

22
arch/arm/mach-mx5/board-mx51_efikamx.c
View file

@ -43,22 +43,22 @@
#define MX51_USB_PLL_DIV_24_MHZ 0x01
#define EFIKAMX_PCBID0 (2*32 + 16)
#define EFIKAMX_PCBID1 (2*32 + 17)
#define EFIKAMX_PCBID2 (2*32 + 11)
#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16)
#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17)
#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11)
#define EFIKAMX_BLUE_LED (2*32 + 13)
#define EFIKAMX_GREEN_LED (2*32 + 14)
#define EFIKAMX_RED_LED (2*32 + 15)
#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13)
#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14)
#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15)
#define EFIKAMX_POWER_KEY (1*32 + 31)
#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31)
#define EFIKAMX_SPI_CS0 (3*32 + 24)
#define EFIKAMX_SPI_CS1 (3*32 + 25)
#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
/* board 1.1 doesn't have same reset gpio */
#define EFIKAMX_RESET1_1 (2*32 + 2)
#define EFIKAMX_RESET (0*32 + 4)
#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2)
#define EFIKAMX_RESET IMX_GPIO_NR(1, 4)
/* the pci ids pin have pull up. they're driven low according to board id */
#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)

10
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
View file

@ -33,12 +33,12 @@
#include "devices-imx51.h"
#include "devices.h"
#define MBIMX51_TSC2007_GPIO (2*32 + 30)
#define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30)
#define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO)
#define MBIMX51_LED0 (2*32 + 5)
#define MBIMX51_LED1 (2*32 + 6)
#define MBIMX51_LED2 (2*32 + 7)
#define MBIMX51_LED3 (2*32 + 8)
#define MBIMX51_LED0 IMX_GPIO_NR(3, 5)
#define MBIMX51_LED1 IMX_GPIO_NR(3, 6)
#define MBIMX51_LED2 IMX_GPIO_NR(3, 7)
#define MBIMX51_LED3 IMX_GPIO_NR(3, 8)
static struct gpio_led mbimx51_leds[] = {
{

4
arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
View file

@ -70,8 +70,8 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
MX51_PAD_SD1_DATA3__SD1_DATA3,
};
#define GPIO_LED1 (2 * 32 + 30)
#define GPIO_SWITCH1 (2 * 32 + 31)
#define GPIO_LED1 IMX_GPIO_NR(3, 30)
#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31)
static struct gpio_led eukrea_mbimxsd_leds[] = {
{

5
arch/arm/plat-mxc/include/mach/gpio.h
View file

@ -23,6 +23,11 @@
#include <mach/hardware.h>
#include <asm-generic/gpio.h>
/* There's a off-by-one betweem the gpio bank number and the gpiochip */
/* range e.g. GPIO_1_5 is gpio 5 under linux */
#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
/* use gpiolib dispatchers */
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value