mtd: nand: denali: use flag instead of register macro for direction
It is not a good idea to re-use macros that represent a specific register bit field for the transfer direction. It is true that bit 8 indicates the direction for the MAP10 pipeline operation and the data DMA operation, but this is not valid across the IP. Use a simple flag (write: 1, read: 0) for the direction. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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@ -63,9 +63,6 @@ static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
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#define MAIN_ACCESS 0x42
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#define MAIN_SPARE_ACCESS 0x43
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#define DENALI_READ 0
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#define DENALI_WRITE 0x100
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/*
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* this is a helper macro that allows us to
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* format the bank into the proper bits for the controller
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@ -339,7 +336,7 @@ static int denali_dev_ready(struct mtd_info *mtd)
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*/
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static int denali_send_pipeline_cmd(struct denali_nand_info *denali, int page,
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bool ecc_en, bool transfer_spare,
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int access_type, int op)
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int access_type, int write)
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{
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int status = PASS;
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uint32_t addr, cmd;
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@ -350,17 +347,17 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, int page,
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addr = BANK(denali->flash_bank) | page;
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if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
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if (write && access_type != SPARE_ACCESS) {
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cmd = MODE_01 | addr;
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iowrite32(cmd, denali->flash_mem);
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} else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
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} else if (write && access_type == SPARE_ACCESS) {
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/* read spare area */
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cmd = MODE_10 | addr;
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index_addr(denali, cmd, access_type);
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cmd = MODE_01 | addr;
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iowrite32(cmd, denali->flash_mem);
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} else if (op == DENALI_READ) {
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} else {
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/* setup page read request for access type */
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cmd = MODE_10 | addr;
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index_addr(denali, cmd, access_type);
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@ -422,7 +419,7 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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int status = 0;
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if (denali_send_pipeline_cmd(denali, page, false, false, SPARE_ACCESS,
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DENALI_WRITE) == PASS) {
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1) == PASS) {
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write_data_to_flash_mem(denali, buf, mtd->oobsize);
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/* wait for operation to complete */
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@ -447,7 +444,7 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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uint32_t irq_status, addr, cmd;
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if (denali_send_pipeline_cmd(denali, page, false, true, SPARE_ACCESS,
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DENALI_READ) == PASS) {
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0) == PASS) {
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read_data_from_flash_mem(denali, buf, mtd->oobsize);
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/*
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@ -633,7 +630,7 @@ static void denali_enable_dma(struct denali_nand_info *denali, bool en)
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}
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static void denali_setup_dma64(struct denali_nand_info *denali,
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dma_addr_t dma_addr, int page, int op)
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dma_addr_t dma_addr, int page, int write)
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{
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uint32_t mode;
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const int page_count = 1;
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@ -646,7 +643,8 @@ static void denali_setup_dma64(struct denali_nand_info *denali,
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* 1. setup transfer type, interrupt when complete,
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* burst len = 64 bytes, the number of pages
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*/
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index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count);
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index_addr(denali, mode,
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0x01002000 | (64 << 16) | (write << 8) | page_count);
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/* 2. set memory low address */
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index_addr(denali, mode, dma_addr);
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@ -656,7 +654,7 @@ static void denali_setup_dma64(struct denali_nand_info *denali,
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}
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static void denali_setup_dma32(struct denali_nand_info *denali,
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dma_addr_t dma_addr, int page, int op)
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dma_addr_t dma_addr, int page, int write)
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{
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uint32_t mode;
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const int page_count = 1;
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@ -666,7 +664,7 @@ static void denali_setup_dma32(struct denali_nand_info *denali,
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/* DMA is a four step process */
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/* 1. setup transfer type and # of pages */
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index_addr(denali, mode | page, 0x2000 | op | page_count);
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index_addr(denali, mode | page, 0x2000 | (write << 8) | page_count);
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/* 2. set memory high address bits 23:8 */
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index_addr(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
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@ -679,12 +677,12 @@ static void denali_setup_dma32(struct denali_nand_info *denali,
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}
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static void denali_setup_dma(struct denali_nand_info *denali,
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dma_addr_t dma_addr, int page, int op)
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dma_addr_t dma_addr, int page, int write)
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{
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if (denali->caps & DENALI_CAP_DMA_64BIT)
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denali_setup_dma64(denali, dma_addr, page, op);
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denali_setup_dma64(denali, dma_addr, page, write);
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else
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denali_setup_dma32(denali, dma_addr, page, op);
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denali_setup_dma32(denali, dma_addr, page, write);
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}
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/*
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@ -723,7 +721,7 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
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denali_reset_irq(denali);
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denali_enable_dma(denali, true);
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denali_setup_dma(denali, addr, page, DENALI_WRITE);
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denali_setup_dma(denali, addr, page, 1);
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/* wait for operation to complete */
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irq_status = denali_wait_for_irq(denali, irq_mask);
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@ -805,7 +803,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
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dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
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denali_reset_irq(denali);
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denali_setup_dma(denali, addr, page, DENALI_READ);
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denali_setup_dma(denali, addr, page, 0);
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/* wait for operation to complete */
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irq_status = denali_wait_for_irq(denali, irq_mask);
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@ -848,7 +846,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
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dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
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denali_reset_irq(denali);
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denali_setup_dma(denali, addr, page, DENALI_READ);
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denali_setup_dma(denali, addr, page, 0);
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/* wait for operation to complete */
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irq_status = denali_wait_for_irq(denali, irq_mask);
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