dt-bindings: dp83867: Convert fifo-depth to common fifo-depth and make optional
Convert the ti,fifo-depth from a TI specific property to the common tx-fifo-depth property. Also add support for the rx-fifo-depth. These are optional properties for this device and if these are not available then the fifo depths are set to device default values. Signed-off-by: Dan Murphy <dmurphy@ti.com> Reported-by: Adrian Bunk <bunk@kernel.org> CC: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -8,8 +8,6 @@ Required properties:
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- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
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for applicable values. Required only if interface type is
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PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID
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- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
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for applicable values
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Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock delays
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will be left at their default values, as set by the PHY's pin strapping.
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@ -42,6 +40,14 @@ Optional property:
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Some MACs work with differential SGMII clock.
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See data manual for details.
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- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
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for applicable values (deprecated)
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-tx-fifo-depth - As defined in the ethernet-controller.yaml. Values for
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the depth can be found in dt-bindings/net/ti-dp83867.h
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-rx-fifo-depth - As defined in the ethernet-controller.yaml. Values for
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the depth can be found in dt-bindings/net/ti-dp83867.h
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Note: ti,min-output-impedance and ti,max-output-impedance are mutually
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exclusive. When both properties are present ti,max-output-impedance
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takes precedence.
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@ -55,7 +61,7 @@ Example:
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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Datasheet can be found:
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