Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] cevt-txx9: Reset timer counter on initialization [MIPS] IP22: Fix crashes due to wrong L1_CACHE_BYTES [MIPS] IP32: Fix unexpected irq 71
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commit
97055a9157
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@ -1006,7 +1006,7 @@ config BOOT_ELF32
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config MIPS_L1_CACHE_SHIFT
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config MIPS_L1_CACHE_SHIFT
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int
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int
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default "4" if MACH_DECSTATION
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default "4" if MACH_DECSTATION
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default "7" if SGI_IP27 || SGI_IP28 || SNI_RM
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default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
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default "4" if PMC_MSP4200_EVAL
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default "4" if PMC_MSP4200_EVAL
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default "5"
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default "5"
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@ -161,6 +161,9 @@ void __init txx9_tmr_init(unsigned long baseaddr)
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struct txx9_tmr_reg __iomem *tmrptr;
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struct txx9_tmr_reg __iomem *tmrptr;
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tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
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tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
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/* Start once to make CounterResetEnable effective */
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__raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);
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/* Stop and reset the counter */
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__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
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__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
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__raw_writel(0, &tmrptr->tisr);
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__raw_writel(0, &tmrptr->tisr);
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__raw_writel(0xffffffff, &tmrptr->cpra);
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__raw_writel(0xffffffff, &tmrptr->cpra);
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@ -425,6 +425,11 @@ static void ip32_irq0(void)
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BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
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BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
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crime_int = crime->istat & crime_mask;
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crime_int = crime->istat & crime_mask;
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/* crime sometime delivers spurious interrupts, ignore them */
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if (unlikely(crime_int == 0))
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return;
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irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
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irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
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if (crime_int & CRIME_MACEISA_INT_MASK) {
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if (crime_int & CRIME_MACEISA_INT_MASK) {
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