Some GPIO fixes for the v3.19 series:
- Three patches fixing IRQ handling for the DLN2 - Null pointer handling for grgpio -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUtEIkAAoJEEEQszewGV1zQdoQAIc/f55GeYEHaB5o/H944uDP 3QW7UEwTWgtnjJNE415u6NzM9zLh1EMhpuYx8fcW54gZe/VNRmilxcKP9qREbDs/ J4WNDVa0Z44XijZMlUcVwGIZPtg1pP2ShwmRxL3RPqnxG8uk/KVQFWbAGt4w5FHG uKNq21ZyQ5bKyQOJgh+i9ArgJz89MQz47nCn3wIwFlcx+1vZc33Td7g7txAB5Toy mAj4t5Up6daLKff3IA+DqfYObeRrTwQTFPOYK3PpjpAokAZiILilj3nuGmH76VAI KyqHoMk7cgpfcZLNpIofGGxAzbdbpnXXshZ4lFI1LgA56GfQhJt6MgNVGnTv6nA+ A8U7Qhip+F49Wreengh1OT5V9l1PDgjfdRUunZXfrQb3VNwQPqtSzPt/OTyRZRAj nc/lIGSJx9lXaZBqGSjDADiC8NdDHerDovboWVttThPkh3skqj7ogDmvu5k41ZVk DYmTHK2o3d2AmjHwMYX8ZQ1FnDOpVBpemkOluB5LsicnD7/2K2J63C9qn52lRF4T DAPel6YhTDDqt4zGjGsLSlgb8f1DF7xY2iMik18t1pFyH+N/NnffIAx3KqahG0+E nhgFFT6SbuEY/yt1G0zb/jKLIfbntzqNElqYnsRpd2HYU4I+vjNhxLsWxh1/bGth lRdCNadVhJSxvZkS8X6c =yUgH -----END PGP SIGNATURE----- Merge tag 'gpio-v3.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull gpio fixes from Linus Walleij: "Here are some GPIO fixes, mainly affecting the DLN2 IRQ handling. Nothing special about them, just fixes: - Three patches fixing IRQ handling for the DLN2 - Null pointer handling for grgpio" * tag 'gpio-v3.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: gpio: dln2: use bus_sync_unlock instead of scheduling work gpio: grgpio: Avoid potential NULL pointer dereference gpio: dln2: Fix gpio output value in dln2_gpio_direction_output() gpio: dln2: fix issue when an IRQ is unmasked then enabledhifive-unleashed-5.1
Linus Torvalds
commit
971780b701
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@ -47,13 +47,6 @@
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#define DLN2_GPIO_MAX_PINS 32
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struct dln2_irq_work {
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struct work_struct work;
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struct dln2_gpio *dln2;
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int pin;
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int type;
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};
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struct dln2_gpio {
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struct platform_device *pdev;
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struct gpio_chip gpio;
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@ -64,10 +57,12 @@ struct dln2_gpio {
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*/
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DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);
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DECLARE_BITMAP(irqs_masked, DLN2_GPIO_MAX_PINS);
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DECLARE_BITMAP(irqs_enabled, DLN2_GPIO_MAX_PINS);
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DECLARE_BITMAP(irqs_pending, DLN2_GPIO_MAX_PINS);
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struct dln2_irq_work *irq_work;
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/* active IRQs - not synced to hardware */
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DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS);
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/* active IRQS - synced to hardware */
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DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS);
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int irq_type[DLN2_GPIO_MAX_PINS];
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struct mutex irq_lock;
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};
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struct dln2_gpio_pin {
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@ -141,16 +136,16 @@ static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
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return !!ret;
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}
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static void dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
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unsigned int pin, int value)
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static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
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unsigned int pin, int value)
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{
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struct dln2_gpio_pin_val req = {
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.pin = cpu_to_le16(pin),
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.value = value,
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};
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dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
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sizeof(req));
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return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
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sizeof(req));
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}
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#define DLN2_GPIO_DIRECTION_IN 0
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@ -267,6 +262,13 @@ static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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struct dln2_gpio *dln2 = container_of(chip, struct dln2_gpio, gpio);
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int ret;
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ret = dln2_gpio_pin_set_out_val(dln2, offset, value);
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if (ret < 0)
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return ret;
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return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
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}
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@ -297,36 +299,13 @@ static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
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&req, sizeof(req));
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}
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static void dln2_irq_work(struct work_struct *w)
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{
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struct dln2_irq_work *iw = container_of(w, struct dln2_irq_work, work);
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struct dln2_gpio *dln2 = iw->dln2;
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u8 type = iw->type & DLN2_GPIO_EVENT_MASK;
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if (test_bit(iw->pin, dln2->irqs_enabled))
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dln2_gpio_set_event_cfg(dln2, iw->pin, type, 0);
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else
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dln2_gpio_set_event_cfg(dln2, iw->pin, DLN2_GPIO_EVENT_NONE, 0);
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}
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static void dln2_irq_enable(struct irq_data *irqd)
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static void dln2_irq_unmask(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
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int pin = irqd_to_hwirq(irqd);
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set_bit(pin, dln2->irqs_enabled);
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schedule_work(&dln2->irq_work[pin].work);
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}
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static void dln2_irq_disable(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
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int pin = irqd_to_hwirq(irqd);
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clear_bit(pin, dln2->irqs_enabled);
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schedule_work(&dln2->irq_work[pin].work);
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set_bit(pin, dln2->unmasked_irqs);
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}
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static void dln2_irq_mask(struct irq_data *irqd)
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@ -335,27 +314,7 @@ static void dln2_irq_mask(struct irq_data *irqd)
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struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
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int pin = irqd_to_hwirq(irqd);
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set_bit(pin, dln2->irqs_masked);
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}
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static void dln2_irq_unmask(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
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struct device *dev = dln2->gpio.dev;
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int pin = irqd_to_hwirq(irqd);
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if (test_and_clear_bit(pin, dln2->irqs_pending)) {
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int irq;
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irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
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if (!irq) {
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dev_err(dev, "pin %d not mapped to IRQ\n", pin);
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return;
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}
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generic_handle_irq(irq);
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}
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clear_bit(pin, dln2->unmasked_irqs);
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}
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static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
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@ -366,19 +325,19 @@ static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_HIGH;
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dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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dln2->irq_work[pin].type = DLN2_GPIO_EVENT_LVL_LOW;
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dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE;
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dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE;
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break;
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case IRQ_TYPE_EDGE_RISING:
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dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_RISING;
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dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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dln2->irq_work[pin].type = DLN2_GPIO_EVENT_CHANGE_FALLING;
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dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING;
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break;
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default:
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return -EINVAL;
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@ -387,13 +346,50 @@ static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
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return 0;
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}
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static void dln2_irq_bus_lock(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
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mutex_lock(&dln2->irq_lock);
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}
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static void dln2_irq_bus_unlock(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct dln2_gpio *dln2 = container_of(gc, struct dln2_gpio, gpio);
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int pin = irqd_to_hwirq(irqd);
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int enabled, unmasked;
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unsigned type;
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int ret;
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enabled = test_bit(pin, dln2->enabled_irqs);
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unmasked = test_bit(pin, dln2->unmasked_irqs);
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if (enabled != unmasked) {
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if (unmasked) {
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type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK;
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set_bit(pin, dln2->enabled_irqs);
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} else {
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type = DLN2_GPIO_EVENT_NONE;
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clear_bit(pin, dln2->enabled_irqs);
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}
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ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0);
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if (ret)
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dev_err(dln2->gpio.dev, "failed to set event\n");
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}
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mutex_unlock(&dln2->irq_lock);
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}
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static struct irq_chip dln2_gpio_irqchip = {
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.name = "dln2-irq",
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.irq_enable = dln2_irq_enable,
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.irq_disable = dln2_irq_disable,
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.irq_mask = dln2_irq_mask,
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.irq_unmask = dln2_irq_unmask,
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.irq_set_type = dln2_irq_set_type,
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.irq_bus_lock = dln2_irq_bus_lock,
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.irq_bus_sync_unlock = dln2_irq_bus_unlock,
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};
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static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
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return;
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}
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if (!test_bit(pin, dln2->irqs_enabled))
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return;
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if (test_bit(pin, dln2->irqs_masked)) {
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set_bit(pin, dln2->irqs_pending);
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return;
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}
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switch (dln2->irq_work[pin].type) {
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switch (dln2->irq_type[pin]) {
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case DLN2_GPIO_EVENT_CHANGE_RISING:
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if (event->value)
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generic_handle_irq(irq);
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@ -451,7 +440,7 @@ static int dln2_gpio_probe(struct platform_device *pdev)
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struct dln2_gpio *dln2;
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struct device *dev = &pdev->dev;
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int pins;
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int i, ret;
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int ret;
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pins = dln2_gpio_get_pin_count(pdev);
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if (pins < 0) {
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@ -467,15 +456,7 @@ static int dln2_gpio_probe(struct platform_device *pdev)
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if (!dln2)
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return -ENOMEM;
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dln2->irq_work = devm_kcalloc(&pdev->dev, pins,
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sizeof(struct dln2_irq_work), GFP_KERNEL);
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if (!dln2->irq_work)
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return -ENOMEM;
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for (i = 0; i < pins; i++) {
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INIT_WORK(&dln2->irq_work[i].work, dln2_irq_work);
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dln2->irq_work[i].pin = i;
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dln2->irq_work[i].dln2 = dln2;
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}
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mutex_init(&dln2->irq_lock);
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dln2->pdev = pdev;
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@ -529,11 +510,8 @@ out:
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static int dln2_gpio_remove(struct platform_device *pdev)
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{
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struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
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int i;
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dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
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for (i = 0; i < dln2->gpio.ngpio; i++)
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flush_work(&dln2->irq_work[i].work);
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gpiochip_remove(&dln2->gpio);
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return 0;
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@ -441,7 +441,8 @@ static int grgpio_probe(struct platform_device *ofdev)
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err = gpiochip_add(gc);
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if (err) {
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dev_err(&ofdev->dev, "Could not add gpiochip\n");
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irq_domain_remove(priv->domain);
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if (priv->domain)
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irq_domain_remove(priv->domain);
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return err;
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}
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