omapdrm changes for 4.15
* OMAP4 HDMI CEC support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZ3x6oAAoJEPo9qoy8lh71+90P/ikuyunHCwWkyAOuURhKQGnN ibHse7McDCdAAFUbPTSOGqSJfBGOK9I5G754k6btea8kxMBxKfW/n7L7wlbak2F0 YZLfcm6km9ef3mZvsgFqhoc87OuLr/V8Ci395DqlN9JUkK0id/CMOzGScf8uqVxE H79vqy5J8OEQMXoURjutQdw4tT2YbB22UnWyAEUHzjlFEAFkOfO8WDJg0WfLVh50 zU56rZ5YDSDiKlzm6unIvTHmb3mEiD9uPAMcCV9uBPfdF+qNLiJV4qw+p5n6d2CI 9Fo/zmuLDYOGRJfrEKggqFuALCQqv1Sl/CzvfE1orjH7O93GLgUbZ6jLViSLr54i JV7qwh9/h85Z+eAh+zEZpG7tvZHCm/ONsJ5CgTeu6bE5VhFdpfDDJQbXgph4PRBJ Y5P52/wsLv9Hn+X/4iV8pzftFzmUUH4Suzv8FPi/ABzhcS77ldFyyqELi/VqwKS0 2DBDS5doOnfoXEEJFugS1hQviRCkhXUrZEK63GhFyC2B/ZJgK+C1ejnz8L74b1r+ mgD0Jhi9DdPIQ4PEX39CNucYIu4aX4dKNNm/LhzHMo3TtcGUSLLf3JpqjjpfWjKg tW9Qxb7pkIkE1m9vr7tk6BD7steLSYAK0YTbwtUp5jwwivBWqmWCWPL76Py9Tc79 cyxAr+JQaaWVcwPIniuh =pNKU -----END PGP SIGNATURE----- Merge tag 'omapdrm-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next omapdrm changes for 4.15 * OMAP4 HDMI CEC support * tag 'omapdrm-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux: omapdrm: omapdss_hdmi_ops: add lost_hotplug op omapdrm: hdmi4: hook up the HDMI CEC support omapdrm: hdmi4_cec: add OMAP4 HDMI CEC support omapdrm: hdmi4: refcount hdmi_power_on/off_core omapdrm: hdmi4: move hdmi4_core_powerdown_disable to hdmi_power_on_core() omapdrm: hdmi4: prepare irq handling for HDMI CEC support omapdrm: hdmi4: make low-level functions available omapdrm: hdmi.h: extend hdmi_core_data with CEC fields omapdrm: encoder-tpd12s015: keep ls_oe_gpio high
This commit is contained in:
commit
972805c137
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@ -165,11 +165,15 @@ static bool hdmic_detect(struct omap_dss_device *dssdev)
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{
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{
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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struct omap_dss_device *in = ddata->in;
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struct omap_dss_device *in = ddata->in;
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bool connected;
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if (gpio_is_valid(ddata->hpd_gpio))
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if (gpio_is_valid(ddata->hpd_gpio))
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return gpio_get_value_cansleep(ddata->hpd_gpio);
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connected = gpio_get_value_cansleep(ddata->hpd_gpio);
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else
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else
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return in->ops.hdmi->detect(in);
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connected = in->ops.hdmi->detect(in);
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if (!connected && in->ops.hdmi->lost_hotplug)
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in->ops.hdmi->lost_hotplug(in);
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return connected;
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}
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}
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static int hdmic_register_hpd_cb(struct omap_dss_device *dssdev,
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static int hdmic_register_hpd_cb(struct omap_dss_device *dssdev,
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@ -51,6 +51,8 @@ static int tpd_connect(struct omap_dss_device *dssdev,
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dssdev->dst = dst;
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dssdev->dst = dst;
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gpiod_set_value_cansleep(ddata->ct_cp_hpd_gpio, 1);
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gpiod_set_value_cansleep(ddata->ct_cp_hpd_gpio, 1);
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gpiod_set_value_cansleep(ddata->ls_oe_gpio, 1);
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/* DC-DC converter needs at max 300us to get to 90% of 5V */
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/* DC-DC converter needs at max 300us to get to 90% of 5V */
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udelay(300);
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udelay(300);
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@ -69,6 +71,7 @@ static void tpd_disconnect(struct omap_dss_device *dssdev,
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return;
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return;
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gpiod_set_value_cansleep(ddata->ct_cp_hpd_gpio, 0);
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gpiod_set_value_cansleep(ddata->ct_cp_hpd_gpio, 0);
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gpiod_set_value_cansleep(ddata->ls_oe_gpio, 0);
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dst->src = NULL;
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dst->src = NULL;
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dssdev->dst = NULL;
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dssdev->dst = NULL;
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@ -146,25 +149,22 @@ static int tpd_read_edid(struct omap_dss_device *dssdev,
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{
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{
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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struct omap_dss_device *in = ddata->in;
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struct omap_dss_device *in = ddata->in;
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int r;
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if (!gpiod_get_value_cansleep(ddata->hpd_gpio))
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if (!gpiod_get_value_cansleep(ddata->hpd_gpio))
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return -ENODEV;
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return -ENODEV;
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gpiod_set_value_cansleep(ddata->ls_oe_gpio, 1);
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return in->ops.hdmi->read_edid(in, edid, len);
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r = in->ops.hdmi->read_edid(in, edid, len);
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gpiod_set_value_cansleep(ddata->ls_oe_gpio, 0);
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return r;
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}
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}
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static bool tpd_detect(struct omap_dss_device *dssdev)
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static bool tpd_detect(struct omap_dss_device *dssdev)
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{
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{
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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struct panel_drv_data *ddata = to_panel_data(dssdev);
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struct omap_dss_device *in = ddata->in;
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bool connected = gpiod_get_value_cansleep(ddata->hpd_gpio);
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return gpiod_get_value_cansleep(ddata->hpd_gpio);
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if (!connected && in->ops.hdmi->lost_hotplug)
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in->ops.hdmi->lost_hotplug(in);
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return connected;
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}
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}
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static int tpd_register_hpd_cb(struct omap_dss_device *dssdev,
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static int tpd_register_hpd_cb(struct omap_dss_device *dssdev,
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@ -65,6 +65,14 @@ config OMAP4_DSS_HDMI
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help
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help
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HDMI support for OMAP4 based SoCs.
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HDMI support for OMAP4 based SoCs.
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config OMAP4_DSS_HDMI_CEC
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bool "Enable HDMI CEC support for OMAP4"
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depends on OMAP4_DSS_HDMI
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select CEC_CORE
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default y
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---help---
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When selected the HDMI transmitter will support the CEC feature.
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config OMAP5_DSS_HDMI
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config OMAP5_DSS_HDMI
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bool "HDMI support for OMAP5"
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bool "HDMI support for OMAP5"
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default n
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default n
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@ -14,5 +14,6 @@ omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
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omapdss-$(CONFIG_OMAP2_DSS_HDMI_COMMON) += hdmi_common.o hdmi_wp.o hdmi_pll.o \
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omapdss-$(CONFIG_OMAP2_DSS_HDMI_COMMON) += hdmi_common.o hdmi_wp.o hdmi_pll.o \
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hdmi_phy.o
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hdmi_phy.o
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omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi4.o hdmi4_core.o
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omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi4.o hdmi4_core.o
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omapdss-$(CONFIG_OMAP4_DSS_HDMI_CEC) += hdmi4_cec.o
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omapdss-$(CONFIG_OMAP5_DSS_HDMI) += hdmi5.o hdmi5_core.o
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omapdss-$(CONFIG_OMAP5_DSS_HDMI) += hdmi5.o hdmi5_core.o
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ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG
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ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG
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@ -24,6 +24,7 @@
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/hdmi.h>
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#include <linux/hdmi.h>
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#include <sound/omap-hdmi-audio.h>
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#include <sound/omap-hdmi-audio.h>
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#include <media/cec.h>
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#include "omapdss.h"
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#include "omapdss.h"
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#include "dss.h"
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#include "dss.h"
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@ -264,6 +265,10 @@ struct hdmi_core_data {
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void __iomem *base;
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void __iomem *base;
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bool cts_swmode;
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bool cts_swmode;
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bool audio_use_mclk;
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bool audio_use_mclk;
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struct hdmi_wp_data *wp;
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unsigned int core_pwr_cnt;
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struct cec_adapter *adap;
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};
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};
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static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
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static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
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@ -373,7 +378,7 @@ struct omap_hdmi {
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bool audio_configured;
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bool audio_configured;
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struct omap_dss_audio audio_config;
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struct omap_dss_audio audio_config;
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/* This lock should be taken when booleans bellow are touched. */
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/* This lock should be taken when booleans below are touched. */
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spinlock_t audio_playing_lock;
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spinlock_t audio_playing_lock;
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bool audio_playing;
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bool audio_playing;
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bool display_enabled;
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bool display_enabled;
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@ -36,9 +36,11 @@
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_graph.h>
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#include <linux/of_graph.h>
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#include <sound/omap-hdmi-audio.h>
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#include <sound/omap-hdmi-audio.h>
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#include <media/cec.h>
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#include "omapdss.h"
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#include "omapdss.h"
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#include "hdmi4_core.h"
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#include "hdmi4_core.h"
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#include "hdmi4_cec.h"
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#include "dss.h"
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#include "dss.h"
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#include "hdmi.h"
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#include "hdmi.h"
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@ -70,7 +72,8 @@ static void hdmi_runtime_put(void)
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static irqreturn_t hdmi_irq_handler(int irq, void *data)
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static irqreturn_t hdmi_irq_handler(int irq, void *data)
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{
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{
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struct hdmi_wp_data *wp = data;
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struct omap_hdmi *hdmi = data;
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struct hdmi_wp_data *wp = &hdmi->wp;
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u32 irqstatus;
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u32 irqstatus;
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irqstatus = hdmi_wp_get_irqstatus(wp);
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irqstatus = hdmi_wp_get_irqstatus(wp);
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@ -95,6 +98,13 @@ static irqreturn_t hdmi_irq_handler(int irq, void *data)
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} else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
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} else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
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}
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}
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if (irqstatus & HDMI_IRQ_CORE) {
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u32 intr4 = hdmi_read_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4);
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hdmi_write_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4, intr4);
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if (intr4 & 8)
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hdmi4_cec_irq(&hdmi->core);
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}
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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@ -123,14 +133,19 @@ static int hdmi_power_on_core(struct omap_dss_device *dssdev)
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{
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{
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int r;
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int r;
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if (hdmi.core.core_pwr_cnt++)
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return 0;
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r = regulator_enable(hdmi.vdda_reg);
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r = regulator_enable(hdmi.vdda_reg);
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if (r)
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if (r)
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return r;
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goto err_reg_enable;
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r = hdmi_runtime_get();
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r = hdmi_runtime_get();
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if (r)
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if (r)
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goto err_runtime_get;
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goto err_runtime_get;
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hdmi4_core_powerdown_disable(&hdmi.core);
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/* Make selection of HDMI in DSS */
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/* Make selection of HDMI in DSS */
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dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
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dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
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@ -140,12 +155,17 @@ static int hdmi_power_on_core(struct omap_dss_device *dssdev)
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err_runtime_get:
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err_runtime_get:
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regulator_disable(hdmi.vdda_reg);
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regulator_disable(hdmi.vdda_reg);
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err_reg_enable:
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hdmi.core.core_pwr_cnt--;
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return r;
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return r;
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}
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}
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static void hdmi_power_off_core(struct omap_dss_device *dssdev)
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static void hdmi_power_off_core(struct omap_dss_device *dssdev)
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{
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{
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if (--hdmi.core.core_pwr_cnt)
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return;
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hdmi.core_enabled = false;
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hdmi.core_enabled = false;
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hdmi_runtime_put();
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hdmi_runtime_put();
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@ -166,8 +186,8 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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return r;
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return r;
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/* disable and clear irqs */
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/* disable and clear irqs */
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hdmi_wp_clear_irqenable(wp, 0xffffffff);
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hdmi_wp_clear_irqenable(wp, ~HDMI_IRQ_CORE);
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hdmi_wp_set_irqstatus(wp, 0xffffffff);
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hdmi_wp_set_irqstatus(wp, ~HDMI_IRQ_CORE);
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vm = &hdmi.cfg.vm;
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vm = &hdmi.cfg.vm;
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@ -242,7 +262,7 @@ static void hdmi_power_off_full(struct omap_dss_device *dssdev)
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{
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{
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enum omap_channel channel = dssdev->dispc_channel;
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enum omap_channel channel = dssdev->dispc_channel;
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hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
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hdmi_wp_clear_irqenable(&hdmi.wp, ~HDMI_IRQ_CORE);
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hdmi_wp_video_stop(&hdmi.wp);
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hdmi_wp_video_stop(&hdmi.wp);
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@ -393,11 +413,11 @@ static void hdmi_display_disable(struct omap_dss_device *dssdev)
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mutex_unlock(&hdmi.lock);
|
mutex_unlock(&hdmi.lock);
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}
|
}
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||||||
|
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static int hdmi_core_enable(struct omap_dss_device *dssdev)
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int hdmi4_core_enable(struct omap_dss_device *dssdev)
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{
|
{
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int r = 0;
|
int r = 0;
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||||||
|
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DSSDBG("ENTER omapdss_hdmi_core_enable\n");
|
DSSDBG("ENTER omapdss_hdmi4_core_enable\n");
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||||||
|
|
||||||
mutex_lock(&hdmi.lock);
|
mutex_lock(&hdmi.lock);
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||||||
|
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||||||
|
@ -415,9 +435,9 @@ err0:
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||||||
return r;
|
return r;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void hdmi_core_disable(struct omap_dss_device *dssdev)
|
void hdmi4_core_disable(struct omap_dss_device *dssdev)
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{
|
{
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||||||
DSSDBG("Enter omapdss_hdmi_core_disable\n");
|
DSSDBG("Enter omapdss_hdmi4_core_disable\n");
|
||||||
|
|
||||||
mutex_lock(&hdmi.lock);
|
mutex_lock(&hdmi.lock);
|
||||||
|
|
||||||
|
@ -475,19 +495,28 @@ static int hdmi_read_edid(struct omap_dss_device *dssdev,
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||||||
need_enable = hdmi.core_enabled == false;
|
need_enable = hdmi.core_enabled == false;
|
||||||
|
|
||||||
if (need_enable) {
|
if (need_enable) {
|
||||||
r = hdmi_core_enable(dssdev);
|
r = hdmi4_core_enable(dssdev);
|
||||||
if (r)
|
if (r)
|
||||||
return r;
|
return r;
|
||||||
}
|
}
|
||||||
|
|
||||||
r = read_edid(edid, len);
|
r = read_edid(edid, len);
|
||||||
|
if (r >= 256)
|
||||||
|
hdmi4_cec_set_phys_addr(&hdmi.core,
|
||||||
|
cec_get_edid_phys_addr(edid, r, NULL));
|
||||||
|
else
|
||||||
|
hdmi4_cec_set_phys_addr(&hdmi.core, CEC_PHYS_ADDR_INVALID);
|
||||||
if (need_enable)
|
if (need_enable)
|
||||||
hdmi_core_disable(dssdev);
|
hdmi4_core_disable(dssdev);
|
||||||
|
|
||||||
return r;
|
return r;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void hdmi_lost_hotplug(struct omap_dss_device *dssdev)
|
||||||
|
{
|
||||||
|
hdmi4_cec_set_phys_addr(&hdmi.core, CEC_PHYS_ADDR_INVALID);
|
||||||
|
}
|
||||||
|
|
||||||
static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
|
static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
|
||||||
const struct hdmi_avi_infoframe *avi)
|
const struct hdmi_avi_infoframe *avi)
|
||||||
{
|
{
|
||||||
|
@ -514,6 +543,7 @@ static const struct omapdss_hdmi_ops hdmi_ops = {
|
||||||
.get_timings = hdmi_display_get_timings,
|
.get_timings = hdmi_display_get_timings,
|
||||||
|
|
||||||
.read_edid = hdmi_read_edid,
|
.read_edid = hdmi_read_edid,
|
||||||
|
.lost_hotplug = hdmi_lost_hotplug,
|
||||||
.set_infoframe = hdmi_set_infoframe,
|
.set_infoframe = hdmi_set_infoframe,
|
||||||
.set_hdmi_mode = hdmi_set_hdmi_mode,
|
.set_hdmi_mode = hdmi_set_hdmi_mode,
|
||||||
};
|
};
|
||||||
|
@ -715,6 +745,10 @@ static int hdmi4_bind(struct device *dev, struct device *master, void *data)
|
||||||
if (r)
|
if (r)
|
||||||
goto err;
|
goto err;
|
||||||
|
|
||||||
|
r = hdmi4_cec_init(pdev, &hdmi.core, &hdmi.wp);
|
||||||
|
if (r)
|
||||||
|
goto err;
|
||||||
|
|
||||||
irq = platform_get_irq(pdev, 0);
|
irq = platform_get_irq(pdev, 0);
|
||||||
if (irq < 0) {
|
if (irq < 0) {
|
||||||
DSSERR("platform_get_irq failed\n");
|
DSSERR("platform_get_irq failed\n");
|
||||||
|
@ -724,7 +758,7 @@ static int hdmi4_bind(struct device *dev, struct device *master, void *data)
|
||||||
|
|
||||||
r = devm_request_threaded_irq(&pdev->dev, irq,
|
r = devm_request_threaded_irq(&pdev->dev, irq,
|
||||||
NULL, hdmi_irq_handler,
|
NULL, hdmi_irq_handler,
|
||||||
IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
|
IRQF_ONESHOT, "OMAP HDMI", &hdmi);
|
||||||
if (r) {
|
if (r) {
|
||||||
DSSERR("HDMI IRQ request failed\n");
|
DSSERR("HDMI IRQ request failed\n");
|
||||||
goto err;
|
goto err;
|
||||||
|
@ -759,6 +793,8 @@ static void hdmi4_unbind(struct device *dev, struct device *master, void *data)
|
||||||
|
|
||||||
hdmi_uninit_output(pdev);
|
hdmi_uninit_output(pdev);
|
||||||
|
|
||||||
|
hdmi4_cec_uninit(&hdmi.core);
|
||||||
|
|
||||||
hdmi_pll_uninit(&hdmi.pll);
|
hdmi_pll_uninit(&hdmi.pll);
|
||||||
|
|
||||||
pm_runtime_disable(&pdev->dev);
|
pm_runtime_disable(&pdev->dev);
|
||||||
|
|
381
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
Normal file
381
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
Normal file
|
@ -0,0 +1,381 @@
|
||||||
|
/*
|
||||||
|
* HDMI CEC
|
||||||
|
*
|
||||||
|
* Based on the CEC code from hdmi_ti_4xxx_ip.c from Android.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||||
|
* Authors: Yong Zhi
|
||||||
|
* Mythri pk <mythripk@ti.com>
|
||||||
|
*
|
||||||
|
* Heavily modified to use the linux CEC framework:
|
||||||
|
*
|
||||||
|
* Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you may redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||||
|
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||||
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||||
|
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||||
|
* SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/err.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
#include <linux/platform_device.h>
|
||||||
|
#include <linux/slab.h>
|
||||||
|
|
||||||
|
#include "dss.h"
|
||||||
|
#include "hdmi.h"
|
||||||
|
#include "hdmi4_core.h"
|
||||||
|
#include "hdmi4_cec.h"
|
||||||
|
|
||||||
|
/* HDMI CEC */
|
||||||
|
#define HDMI_CEC_DEV_ID 0x900
|
||||||
|
#define HDMI_CEC_SPEC 0x904
|
||||||
|
|
||||||
|
/* Not really a debug register, more a low-level control register */
|
||||||
|
#define HDMI_CEC_DBG_3 0x91C
|
||||||
|
#define HDMI_CEC_TX_INIT 0x920
|
||||||
|
#define HDMI_CEC_TX_DEST 0x924
|
||||||
|
#define HDMI_CEC_SETUP 0x938
|
||||||
|
#define HDMI_CEC_TX_COMMAND 0x93C
|
||||||
|
#define HDMI_CEC_TX_OPERAND 0x940
|
||||||
|
#define HDMI_CEC_TRANSMIT_DATA 0x97C
|
||||||
|
#define HDMI_CEC_CA_7_0 0x988
|
||||||
|
#define HDMI_CEC_CA_15_8 0x98C
|
||||||
|
#define HDMI_CEC_INT_STATUS_0 0x998
|
||||||
|
#define HDMI_CEC_INT_STATUS_1 0x99C
|
||||||
|
#define HDMI_CEC_INT_ENABLE_0 0x990
|
||||||
|
#define HDMI_CEC_INT_ENABLE_1 0x994
|
||||||
|
#define HDMI_CEC_RX_CONTROL 0x9B0
|
||||||
|
#define HDMI_CEC_RX_COUNT 0x9B4
|
||||||
|
#define HDMI_CEC_RX_CMD_HEADER 0x9B8
|
||||||
|
#define HDMI_CEC_RX_COMMAND 0x9BC
|
||||||
|
#define HDMI_CEC_RX_OPERAND 0x9C0
|
||||||
|
|
||||||
|
#define HDMI_CEC_TX_FIFO_INT_MASK 0x64
|
||||||
|
#define HDMI_CEC_RETRANSMIT_CNT_INT_MASK 0x2
|
||||||
|
|
||||||
|
#define HDMI_CORE_CEC_RETRY 200
|
||||||
|
|
||||||
|
static void hdmi_cec_received_msg(struct hdmi_core_data *core)
|
||||||
|
{
|
||||||
|
u32 cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
|
||||||
|
|
||||||
|
/* While there are CEC frames in the FIFO */
|
||||||
|
while (cnt & 0x70) {
|
||||||
|
/* and the frame doesn't have an error */
|
||||||
|
if (!(cnt & 0x80)) {
|
||||||
|
struct cec_msg msg = {};
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
/* then read the message */
|
||||||
|
msg.len = cnt & 0xf;
|
||||||
|
msg.msg[0] = hdmi_read_reg(core->base,
|
||||||
|
HDMI_CEC_RX_CMD_HEADER);
|
||||||
|
msg.msg[1] = hdmi_read_reg(core->base,
|
||||||
|
HDMI_CEC_RX_COMMAND);
|
||||||
|
for (i = 0; i < msg.len; i++) {
|
||||||
|
unsigned int reg = HDMI_CEC_RX_OPERAND + i * 4;
|
||||||
|
|
||||||
|
msg.msg[2 + i] =
|
||||||
|
hdmi_read_reg(core->base, reg);
|
||||||
|
}
|
||||||
|
msg.len += 2;
|
||||||
|
cec_received_msg(core->adap, &msg);
|
||||||
|
}
|
||||||
|
/* Clear the current frame from the FIFO */
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 1);
|
||||||
|
/* Wait until the current frame is cleared */
|
||||||
|
while (hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL) & 1)
|
||||||
|
udelay(1);
|
||||||
|
/*
|
||||||
|
* Re-read the count register and loop to see if there are
|
||||||
|
* more messages in the FIFO.
|
||||||
|
*/
|
||||||
|
cnt = hdmi_read_reg(core->base, HDMI_CEC_RX_COUNT) & 0xff;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void hdmi_cec_transmit_fifo_empty(struct hdmi_core_data *core, u32 stat1)
|
||||||
|
{
|
||||||
|
if (stat1 & 2) {
|
||||||
|
u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
|
||||||
|
|
||||||
|
cec_transmit_done(core->adap,
|
||||||
|
CEC_TX_STATUS_NACK |
|
||||||
|
CEC_TX_STATUS_MAX_RETRIES,
|
||||||
|
0, (dbg3 >> 4) & 7, 0, 0);
|
||||||
|
} else if (stat1 & 1) {
|
||||||
|
cec_transmit_done(core->adap,
|
||||||
|
CEC_TX_STATUS_ARB_LOST |
|
||||||
|
CEC_TX_STATUS_MAX_RETRIES,
|
||||||
|
0, 0, 0, 0);
|
||||||
|
} else if (stat1 == 0) {
|
||||||
|
cec_transmit_done(core->adap, CEC_TX_STATUS_OK,
|
||||||
|
0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void hdmi4_cec_irq(struct hdmi_core_data *core)
|
||||||
|
{
|
||||||
|
u32 stat0 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0);
|
||||||
|
u32 stat1 = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
|
||||||
|
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0, stat0);
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, stat1);
|
||||||
|
|
||||||
|
if (stat0 & 0x40)
|
||||||
|
REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
|
||||||
|
else if (stat0 & 0x24)
|
||||||
|
hdmi_cec_transmit_fifo_empty(core, stat1);
|
||||||
|
if (stat1 & 2) {
|
||||||
|
u32 dbg3 = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
|
||||||
|
|
||||||
|
cec_transmit_done(core->adap,
|
||||||
|
CEC_TX_STATUS_NACK |
|
||||||
|
CEC_TX_STATUS_MAX_RETRIES,
|
||||||
|
0, (dbg3 >> 4) & 7, 0, 0);
|
||||||
|
} else if (stat1 & 1) {
|
||||||
|
cec_transmit_done(core->adap,
|
||||||
|
CEC_TX_STATUS_ARB_LOST |
|
||||||
|
CEC_TX_STATUS_MAX_RETRIES,
|
||||||
|
0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
if (stat0 & 0x02)
|
||||||
|
hdmi_cec_received_msg(core);
|
||||||
|
if (stat1 & 0x3)
|
||||||
|
REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool hdmi_cec_clear_tx_fifo(struct cec_adapter *adap)
|
||||||
|
{
|
||||||
|
struct hdmi_core_data *core = cec_get_drvdata(adap);
|
||||||
|
int retry = HDMI_CORE_CEC_RETRY;
|
||||||
|
int temp;
|
||||||
|
|
||||||
|
REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7);
|
||||||
|
while (retry) {
|
||||||
|
temp = hdmi_read_reg(core->base, HDMI_CEC_DBG_3);
|
||||||
|
if (FLD_GET(temp, 7, 7) == 0)
|
||||||
|
break;
|
||||||
|
retry--;
|
||||||
|
}
|
||||||
|
return retry != 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool hdmi_cec_clear_rx_fifo(struct cec_adapter *adap)
|
||||||
|
{
|
||||||
|
struct hdmi_core_data *core = cec_get_drvdata(adap);
|
||||||
|
int retry = HDMI_CORE_CEC_RETRY;
|
||||||
|
int temp;
|
||||||
|
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_RX_CONTROL, 0x3);
|
||||||
|
retry = HDMI_CORE_CEC_RETRY;
|
||||||
|
while (retry) {
|
||||||
|
temp = hdmi_read_reg(core->base, HDMI_CEC_RX_CONTROL);
|
||||||
|
if (FLD_GET(temp, 1, 0) == 0)
|
||||||
|
break;
|
||||||
|
retry--;
|
||||||
|
}
|
||||||
|
return retry != 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
|
||||||
|
{
|
||||||
|
struct hdmi_core_data *core = cec_get_drvdata(adap);
|
||||||
|
int temp, err;
|
||||||
|
|
||||||
|
if (!enable) {
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0);
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0);
|
||||||
|
REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3);
|
||||||
|
hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE);
|
||||||
|
hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE);
|
||||||
|
hdmi4_core_disable(NULL);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
err = hdmi4_core_enable(NULL);
|
||||||
|
if (err)
|
||||||
|
return err;
|
||||||
|
|
||||||
|
/* Clear TX FIFO */
|
||||||
|
if (!hdmi_cec_clear_tx_fifo(adap)) {
|
||||||
|
pr_err("cec-%s: could not clear TX FIFO\n", adap->name);
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear RX FIFO */
|
||||||
|
if (!hdmi_cec_clear_rx_fifo(adap)) {
|
||||||
|
pr_err("cec-%s: could not clear RX FIFO\n", adap->name);
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear CEC interrupts */
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
|
||||||
|
hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1));
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
|
||||||
|
hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_0));
|
||||||
|
|
||||||
|
/* Enable HDMI core interrupts */
|
||||||
|
hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE);
|
||||||
|
/* Unmask CEC interrupt */
|
||||||
|
REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3);
|
||||||
|
/*
|
||||||
|
* Enable CEC interrupts:
|
||||||
|
* Transmit Buffer Full/Empty Change event
|
||||||
|
* Transmitter FIFO Empty event
|
||||||
|
* Receiver FIFO Not Empty event
|
||||||
|
*/
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_0, 0x26);
|
||||||
|
/*
|
||||||
|
* Enable CEC interrupts:
|
||||||
|
* RX FIFO Overrun Error event
|
||||||
|
* Short Pulse Detected event
|
||||||
|
* Frame Retransmit Count Exceeded event
|
||||||
|
* Start Bit Irregularity event
|
||||||
|
*/
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_INT_ENABLE_1, 0x0f);
|
||||||
|
|
||||||
|
/* cec calibration enable (self clearing) */
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x03);
|
||||||
|
msleep(20);
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_SETUP, 0x04);
|
||||||
|
|
||||||
|
temp = hdmi_read_reg(core->base, HDMI_CEC_SETUP);
|
||||||
|
if (FLD_GET(temp, 4, 4) != 0) {
|
||||||
|
temp = FLD_MOD(temp, 0, 4, 4);
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_SETUP, temp);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If we enabled CEC in middle of a CEC message on the bus,
|
||||||
|
* we could have start bit irregularity and/or short
|
||||||
|
* pulse event. Clear them now.
|
||||||
|
*/
|
||||||
|
temp = hdmi_read_reg(core->base, HDMI_CEC_INT_STATUS_1);
|
||||||
|
temp = FLD_MOD(0x0, 0x5, 2, 0);
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, temp);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
|
||||||
|
{
|
||||||
|
struct hdmi_core_data *core = cec_get_drvdata(adap);
|
||||||
|
u32 v;
|
||||||
|
|
||||||
|
if (log_addr == CEC_LOG_ADDR_INVALID) {
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, 0);
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, 0);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
if (log_addr <= 7) {
|
||||||
|
v = hdmi_read_reg(core->base, HDMI_CEC_CA_7_0);
|
||||||
|
v |= 1 << log_addr;
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_CA_7_0, v);
|
||||||
|
} else {
|
||||||
|
v = hdmi_read_reg(core->base, HDMI_CEC_CA_15_8);
|
||||||
|
v |= 1 << (log_addr - 8);
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_CA_15_8, v);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
|
||||||
|
u32 signal_free_time, struct cec_msg *msg)
|
||||||
|
{
|
||||||
|
struct hdmi_core_data *core = cec_get_drvdata(adap);
|
||||||
|
int temp;
|
||||||
|
u32 i;
|
||||||
|
|
||||||
|
/* Clear TX FIFO */
|
||||||
|
if (!hdmi_cec_clear_tx_fifo(adap)) {
|
||||||
|
pr_err("cec-%s: could not clear TX FIFO for transmit\n",
|
||||||
|
adap->name);
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear TX interrupts */
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_0,
|
||||||
|
HDMI_CEC_TX_FIFO_INT_MASK);
|
||||||
|
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1,
|
||||||
|
HDMI_CEC_RETRANSMIT_CNT_INT_MASK);
|
||||||
|
|
||||||
|
/* Set the retry count */
|
||||||
|
REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4);
|
||||||
|
|
||||||
|
/* Set the initiator addresses */
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_TX_INIT, cec_msg_initiator(msg));
|
||||||
|
|
||||||
|
/* Set destination id */
|
||||||
|
temp = cec_msg_destination(msg);
|
||||||
|
if (msg->len == 1)
|
||||||
|
temp |= 0x80;
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_TX_DEST, temp);
|
||||||
|
if (msg->len == 1)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
/* Setup command and arguments for the command */
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_TX_COMMAND, msg->msg[1]);
|
||||||
|
|
||||||
|
for (i = 0; i < msg->len - 2; i++)
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_TX_OPERAND + i * 4,
|
||||||
|
msg->msg[2 + i]);
|
||||||
|
|
||||||
|
/* Operand count */
|
||||||
|
hdmi_write_reg(core->base, HDMI_CEC_TRANSMIT_DATA,
|
||||||
|
(msg->len - 2) | 0x10);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct cec_adap_ops hdmi_cec_adap_ops = {
|
||||||
|
.adap_enable = hdmi_cec_adap_enable,
|
||||||
|
.adap_log_addr = hdmi_cec_adap_log_addr,
|
||||||
|
.adap_transmit = hdmi_cec_adap_transmit,
|
||||||
|
};
|
||||||
|
|
||||||
|
void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa)
|
||||||
|
{
|
||||||
|
cec_s_phys_addr(core->adap, pa, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
int hdmi4_cec_init(struct platform_device *pdev, struct hdmi_core_data *core,
|
||||||
|
struct hdmi_wp_data *wp)
|
||||||
|
{
|
||||||
|
const u32 caps = CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS |
|
||||||
|
CEC_CAP_PASSTHROUGH | CEC_CAP_RC;
|
||||||
|
unsigned int ret;
|
||||||
|
|
||||||
|
core->adap = cec_allocate_adapter(&hdmi_cec_adap_ops, core,
|
||||||
|
"omap4", caps, CEC_MAX_LOG_ADDRS);
|
||||||
|
ret = PTR_ERR_OR_ZERO(core->adap);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
core->wp = wp;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Initialize CEC clock divider: CEC needs 2MHz clock hence
|
||||||
|
* set the devider to 24 to get 48/24=2MHz clock
|
||||||
|
*/
|
||||||
|
REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);
|
||||||
|
|
||||||
|
ret = cec_register_adapter(core->adap, &pdev->dev);
|
||||||
|
if (ret < 0) {
|
||||||
|
cec_delete_adapter(core->adap);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void hdmi4_cec_uninit(struct hdmi_core_data *core)
|
||||||
|
{
|
||||||
|
cec_unregister_adapter(core->adap);
|
||||||
|
}
|
55
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.h
Normal file
55
drivers/gpu/drm/omapdrm/dss/hdmi4_cec.h
Normal file
|
@ -0,0 +1,55 @@
|
||||||
|
/*
|
||||||
|
* HDMI header definition for OMAP4 HDMI CEC IP
|
||||||
|
*
|
||||||
|
* Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
|
||||||
|
*
|
||||||
|
* This program is free software; you may redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||||
|
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||||
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||||
|
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||||
|
* SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _HDMI4_CEC_H_
|
||||||
|
#define _HDMI4_CEC_H_
|
||||||
|
|
||||||
|
struct hdmi_core_data;
|
||||||
|
struct hdmi_wp_data;
|
||||||
|
struct platform_device;
|
||||||
|
|
||||||
|
/* HDMI CEC funcs */
|
||||||
|
#ifdef CONFIG_OMAP4_DSS_HDMI_CEC
|
||||||
|
void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa);
|
||||||
|
void hdmi4_cec_irq(struct hdmi_core_data *core);
|
||||||
|
int hdmi4_cec_init(struct platform_device *pdev, struct hdmi_core_data *core,
|
||||||
|
struct hdmi_wp_data *wp);
|
||||||
|
void hdmi4_cec_uninit(struct hdmi_core_data *core);
|
||||||
|
#else
|
||||||
|
static inline void hdmi4_cec_set_phys_addr(struct hdmi_core_data *core, u16 pa)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void hdmi4_cec_irq(struct hdmi_core_data *core)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int hdmi4_cec_init(struct platform_device *pdev,
|
||||||
|
struct hdmi_core_data *core,
|
||||||
|
struct hdmi_wp_data *wp)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void hdmi4_cec_uninit(struct hdmi_core_data *core)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
|
@ -208,9 +208,9 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg)
|
||||||
video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
|
video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void hdmi_core_powerdown_disable(struct hdmi_core_data *core)
|
void hdmi4_core_powerdown_disable(struct hdmi_core_data *core)
|
||||||
{
|
{
|
||||||
DSSDBG("Enter hdmi_core_powerdown_disable\n");
|
DSSDBG("Enter hdmi4_core_powerdown_disable\n");
|
||||||
REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x1, 0, 0);
|
REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x1, 0, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -335,9 +335,6 @@ void hdmi4_configure(struct hdmi_core_data *core,
|
||||||
*/
|
*/
|
||||||
hdmi_core_swreset_assert(core);
|
hdmi_core_swreset_assert(core);
|
||||||
|
|
||||||
/* power down off */
|
|
||||||
hdmi_core_powerdown_disable(core);
|
|
||||||
|
|
||||||
v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
|
v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
|
||||||
v_core_cfg.hdmi_dvi = cfg->hdmi_dvi_mode;
|
v_core_cfg.hdmi_dvi = cfg->hdmi_dvi_mode;
|
||||||
|
|
||||||
|
|
|
@ -266,6 +266,10 @@ void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
|
||||||
void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s);
|
void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s);
|
||||||
int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core);
|
int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core);
|
||||||
|
|
||||||
|
int hdmi4_core_enable(struct omap_dss_device *dssdev);
|
||||||
|
void hdmi4_core_disable(struct omap_dss_device *dssdev);
|
||||||
|
void hdmi4_core_powerdown_disable(struct hdmi_core_data *core);
|
||||||
|
|
||||||
int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
|
int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
|
||||||
void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
|
void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
|
||||||
int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
|
int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
|
||||||
|
|
|
@ -395,6 +395,7 @@ struct omapdss_hdmi_ops {
|
||||||
struct videomode *vm);
|
struct videomode *vm);
|
||||||
|
|
||||||
int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
|
int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
|
||||||
|
void (*lost_hotplug)(struct omap_dss_device *dssdev);
|
||||||
bool (*detect)(struct omap_dss_device *dssdev);
|
bool (*detect)(struct omap_dss_device *dssdev);
|
||||||
|
|
||||||
int (*register_hpd_cb)(struct omap_dss_device *dssdev,
|
int (*register_hpd_cb)(struct omap_dss_device *dssdev,
|
||||||
|
|
Loading…
Reference in a new issue