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drm/i915: Ensure the HiZ RAW Stall Optimization is on for Cherryview.

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This is an important optimization for avoiding read-after-write (RAW)
stalls in the HiZ buffer.  Certain workloads would run very slowly with
HiZ enabled, but run much faster with the "hiz=false" driconf option.
With this patch, they run at full speed even with HiZ.

Increases performance in OglVSInstancing by about 2.7x on Braswell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Kenneth Graunke 2015-01-13 12:46:53 -08:00 committed by Daniel Vetter
parent 2701fc4356
commit 973a5b06a0
1 changed files with 5 additions and 0 deletions
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5
drivers/gpu/drm/i915/intel_ringbuffer.c
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@ -846,6 +846,11 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
HDC_FORCE_NON_COHERENT |
HDC_DONOT_FETCH_MEM_WHEN_MASKED);
/* According to the CACHE_MODE_0 default value documentation, some
* CHV platforms disable this optimization by default. Turn it on.
*/
WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
/* Improve HiZ throughput on CHV. */
WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);